Self-tuning cache

Details Self-tuning cache Self-tuning cache

2007-10-16

2007-10-16

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S119000, C711S171000, C711S172000

Reexamination Certificate

active

10759410

ABSTRACT:
The present invention is a system, method and apparatus for self-tuning cache management. In a preferred aspect of the invention, a self-tuning cache can include a primary cache and at least two test caches. A first one of the test caches can have a cache size which is smaller than a size of the primary cache. A second one of the test caches can have a cache size which is greater than the size of the primary cache. A cache engine can be programmed to manage the primary cache and the test caches. importantly, a cache tuner can be coupled to the primary and test caches. The cache tuner can include a configuration for resizing the primary cache when one of the at least two test caches demonstrates cache performance which justifies resizing the primary cache.

REFERENCES:
patent: 4315312 (1982-02-01), Schmidt
patent: 5394531 (1995-02-01), Smith
patent: 5668987 (1997-09-01), Schneider
patent: 5732240 (1998-03-01), Caccavale
patent: 6128701 (2000-10-01), Malcolm et al.
patent: 6952664 (2005-10-01), Lahiri et al.
patent: 2003/0204698 (2003-10-01), Sachedina et al.

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