Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2007-12-11
2007-12-11
Bragdon, Reginald (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S163000
Reexamination Certificate
active
10927170
ABSTRACT:
A buffer output manager facilitates automatic self-triggering output of buffer contents. At least one processes writes control data to at least one buffer, the control data being such that a buffer output trigger address can be determined therefrom. For each buffer to which control data is written, a buffer output manager determines the trigger address of that buffer. At least one process writes data to at least one buffer, including to the trigger address thereof. For each buffer to which data is written to the trigger address, the buffer output manager automatically outputs the contents of that buffer, responsive to the writing of the data to the trigger address.
REFERENCES:
patent: 2002/0095536 (2002-07-01), Emberty et al.
patent: 2005/0055536 (2005-03-01), Ansari
patent: 2005/0182886 (2005-08-01), Edirisooriya et al.
patent: 2005/0286856 (2005-12-01), Aerts
Bragdon Reginald
Dinh Ngoc
Klein O'Neill & Singh, LLP
Qlogic Corporation
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