Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2002-01-22
2003-07-08
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S086000, C327S108000
Reexamination Certificate
active
06590413
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates in general to integrated circuitry, and in particular to methods and circuitry for implementing integrated differential termination resistance with a self-tracking feature that results in a relatively constant resistance value.
Advances in semiconductor processing technology and high speed circuit techniques have made gigabits per second (Gb/s) data rates possible at the integrated circuit level. At the same time reduction in power consumption continues to be a great concern not only for battery-operated portable systems, but for reduction of overall system costs related to packaging and cooling systems. This combination poses a challenging task for the circuit designer, especially when it comes to the interface circuitry. Various data signaling approaches have been developed to address some of these concerns. Low-voltage differential signaling (LVDS), for example, is one signaling technique that provides a low-power, low-voltage and high-speed alternative. LVDS, however, places relatively stringent requirements on the tolerance affecting the input/output (I/O) levels. It requires, for example, that the input termination resistance to stay relatively constant within ±10% of tolerance and under a specific operating range. Termination is needed to prevent unwanted reflections that would corrupt the signal when transmitting signals over distances appreciable with respect to the signal period. It is desirable to provide a self-terminating circuit that incorporates the termination resistance on the same integrated circuit for a more cost-efficient implementation.
To implement such an integrated resistor in the LVDS input buffer using a standard CMOS process technology has been a challenging task and the focus of many research efforts. One approach uses appropriate passive devices such as diffusion or implant resistors, but suffers from process variations, which is normally greater than 15% in both directions. The use of a relatively higher accuracy polysilicon resistor may be restricted as the oxide layer under the polysilicon may not sustain a specified electrostatic discharge (ESD) at an LVDS receiver's inputs. Another approach employs active circuits including pass transistors or transmission gates. The on-resistance of the transistors, however, fluctuates which makes it difficult to meet the relatively wide range of input common-mode voltage level (0 to 2.4V). The on-resistance of the devices is also influenced by the fluctuations in processing, power supply voltage and temperature. Improvements in this regard have been made through dynamic on-chip trimming, but that has also come at the expense of more complexity and device overhead.
There is therefore a need to implement a relatively constant integrated termination resistor that satisfies the requirements of differential signaling with minimum circuit complexity.
BRIEF SUMMARY OF THE INVENTION
The present invention addresses problems associated with implementation of an integrated termination resistor required by differential interconnect signaling technologies such as LVDS. In a specific embodiment, the invention presents a circuit technique for implementing a self-tracking differential termination resistor in standard CMOS process technology. The circuit employs a mechanism that automatically tracks variations on input common-mode voltage level as well as varying device characteristics due to fluctuations in processing, power supply voltage and temperature. It then adjusts the resistance across the two differential input signals in a self-calibrating manner to obtain a substantially constant termination resistance for a given application. In a specific embodiment, the actual resistance is defined with an external reference resistor, independent of other operating conditions.
Accordingly, in one embodiment, the present invention provides an integrated differential termination resistance coupled between a first node and a second node, including: a first resistive element coupled to the first node; a first field effect transistor (FET) coupled between the first resistive element and a common node; a second resistive element coupled to the second node; a second FET coupled between the second resistive element and the common node, wherein source terminals of the first and second FETs couple to the common node; and a termination control circle coupled to gate terminals of the first and second FETs and the common node, and configured to track variations in a resistance value of the termination resistance and to compensate for the variations by adjusting a control voltage at the gate terminals of the first and second FETs. In a more specific embodiment, the termination control circuit includes a replica biasing circuit that adjusts the value of the control voltage in response to variations in a common-mode voltage at the common node.
In another embodiment, the present invention provides a method of implementing a differential termination resistance including coupling source and drain terminals of a field effect transistor (FET) across differential terminals, respectively; operating the FET in a triode region such that its channel provides an adjustable termination resistance; tracking variations in a nominal value of the termination resistance via a replica termination resistance; and adjusting a resistance value of the FET by varying a gate voltage of the FET to compensate for the variations.
The following detailed description and the accompanying drawings provide a better understanding of the nature and advantages of the self-tracking integrated differential termination according to the present invention.
REFERENCES:
patent: 5164663 (1992-11-01), Alcorn
patent: 5359235 (1994-10-01), Coyle et al.
patent: 5374861 (1994-12-01), Kubista
patent: 5726583 (1998-03-01), Kaplinsky
patent: 5864715 (1999-01-01), Zani et al.
patent: 5955911 (1999-09-01), Drost et al.
patent: 6008665 (1999-12-01), Kalb et al.
patent: 6026456 (2000-02-01), Ilkbahar
patent: 6037798 (2000-03-01), Hedberg
patent: 6087847 (2000-07-01), Mooney et al.
patent: 6097208 (2000-08-01), Okajima et al.
patent: 6100713 (2000-08-01), Kalb et al.
patent: 6154060 (2000-11-01), Morriss
patent: 6157206 (2000-12-01), Taylor et al.
patent: 6181157 (2001-01-01), Fiedler
patent: 6329836 (2001-12-01), Drost et al.
patent: 6362644 (2002-03-01), Jeffery et al.
patent: 6411126 (2002-06-01), Tinsley et al.
patent: 6448813 (2002-09-01), Garlepp et al.
LVDS I/O Interface for Gb/s-per-Pin Operation in 0.35-&mgr;m CMOS,Boni, et al.,IEEE Journal of Solid-State Circuits,vol. 36, No. 4, Apr. 2001.
CMOS VLSI Implementation of Gigabyte/Second Computer Network Links,Bendak et al., Dept. of Electrical and Computer Engineering, University of California at San Diego, La Jolla, CA 92093-0407,IEEE International Symposium on Circuits and Systems,1996.
Altera Corporation
Sani Babak S.
Tan Vibol
Townsend and Townsend / and Crew LLP
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