Self-tracking delay-matching write pulse control circuit and met

Details Self-tracking delay-matching write pulse control circuit and met Self-tracking delay-matching write pulse control circuit and met

1996-12-27

1998-02-03

Zarabian, A.

Static information storage and retrieval

Read/write circuit

Signals

365194, 36518902, G11C 700

Patent

active

057152012

ABSTRACT:
A self-tracking write pulse control circuit to determine the time provided to complete a write operation to a memory. A tracking array including at least a first tracking memory cell configured on the memory includes an output and stores a default value. First and second bitlines are coupled to the tracking memory cell. A write multiplexor circuit is coupled to the first and second bitlines and coupled to receive an enable signal which concurrently initiates a write pulse. A write multiplexor circuit writes a different value to the tracking memory cell in response to receiving the enable signal. The output of the tracking memory cell transitions to end the write pulse when the different value has been successfully written to the tracking memory cell.

REFERENCES:
patent: 4727519 (1988-02-01), Morton

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