Self timing write architecture for semiconductor memory and...

Details Self timing write architecture for semiconductor memory and... Self timing write architecture for semiconductor memory and...

2006-12-28

2008-07-22

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

C365S210130

Reexamination Certificate

active

07403433

ABSTRACT:
A self timing write architecture for semiconductor memory and a method for providing the same are provided. The core region of the semiconductor memory comprises of a normal memory cell array and a dummy column. The dummy column comprises of two blocks—block A and block B. Block A is composed of a cluster of N dummy cells in which data is written during write operation. The remaining cells in the dummy column together form block B which is meant for providing load for the dummy bit line. During a write operation, a dummy word line is generated to enable dummy memory cells of block A. The dummy bit line is then made to travel half the number of rows in the normal memory array and then made to return back. A dummy data is then written in all the dummy cells in block A. Simultaneously, a normal memory cell is also accessed and actual data is written into it. As soon as the writing operation is complete, a W-reset signal is generated to indicate successful completion of write operation. Recovery operation for the next cycle is then started.

REFERENCES:
patent: 5596526 (1997-01-01), Assar et al.
patent: 6522567 (2003-02-01), Iwanari

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