Self-timing for a multi-ported memory system

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area

Reexamination Certificate

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C711SE12001, C713S400000

Reexamination Certificate

active

08082401

ABSTRACT:
Multi-ported memory systems (e.g., register files) employ self-timing for operational synchronization. Thus, rather than using a reference clock duty cycle for operational synchronization, as in conventional multi-ported register files, embodiments of the present disclosure employ self-timing for such operational synchronization. According to certain embodiments, self-timing is employed to synchronize all the internal events within the memory so that all the events are spaced in time for appropriate synchronization. For instance, the completion of one event leads to triggering another event, the completion of which leads to triggering another event, and so on. Thus, in one embodiment, the self-timing is achieved by referencing the operational events with the memory (or register file) to each other, rather than to a reference clock duty cycle.

REFERENCES:
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patent: 5596539 (1997-01-01), Passow et al.
patent: 6112295 (2000-08-01), Bhamidipati et al.
patent: 6201757 (2001-03-01), Ward et al.
patent: 2007/0297266 (2007-12-01), Anvar et al.
International Search Report and Written Opinion—PCT/US2010/028508, International Search Authority—Korean Intellectual Property Office—Nov. 4, 2010.

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