Self-timed write reset pulse generation

Details Self-timed write reset pulse generation Self-timed write reset pulse generation

1998-10-30

2000-06-06

Mai, Son

Static information storage and retrieval

Read/write circuit

Signals

36518901, 365190, G11C 700

Patent

active

060727322

ABSTRACT:
A memory, such as a static random access memory (SRAM), includes at least one memory cell. The bit lines for that memory cell are selectively connected to corresponding write bit lines through a column select pass transistor and a selectively blowable fuse. A reset circuit is connected to the same write bit lines through a fuse structure mimic circuit. Responsive to data transitions on the write bit lines, the reset circuit operates to detect the occurrence of a memory operation to the memory cell and generate a reset signal for resetting the memory in preparation for a next write operation. To support substantially simultaneous presentation of write data to both the reset circuit and the memory cell, the fuse structure mimic circuit delays presentation of the write bit line data to the reset circuit. This introduced delay substantially corresponds to a delay in the presentation of the write bit line data to the memory cell resulting from driving the memory cell bit lines through the selectively blowable fuses.

REFERENCES:
patent: 5010519 (1991-04-01), Yoshimoto et al.
patent: 5018111 (1991-05-01), Madland
patent: 5655105 (1997-08-01), McLaury
patent: 5724292 (1998-03-01), Wada
patent: 5808960 (1998-09-01), McClure

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