Self-timed voltage-subtraction sneak current cancellation...

Details Self-timed voltage-subtraction sneak current cancellation... Self-timed voltage-subtraction sneak current cancellation...

2005-10-04

2005-10-04

Ho, Hoai (Department: 2827)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S045000, C365S189070, C365S189090, C365S202000, C365S207000, C365S233100

Reexamination Certificate

active

06952375

ABSTRACT:
A single bit line reference signal path or line is used for both voltage subtraction and self-timing of a second sense that is longer than a first sense in a dual-sense, single-read memory cell. The self-timing mechanism includes an analog circuit.

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patent: 6570440 (2003-05-01), Chow et al.
patent: 2003/0016564 (2003-01-01), Schramm et al.

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