Self-timed sequential access multiport memory

Static information storage and retrieval – Read/write circuit – Serial read/write

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Details

365 78, 36523003, 36523004, 36518905, 36518902, G11C 1300, G11C 700

Patent

active

050273264

ABSTRACT:
A RAM-based FIFO which provides self-timing of the data outputs in read mode. When the data output is not valid, the data output drivers are in a high-impedance condition. Therefore, FIFOs using this RAM-based architecture can readily be combined to provide a wider or deeper FIFO, without introducing any additional delay whatsoever. Small differential delays are preferably introduced in the activation of the output buffers, to avoid noise on power supply lines.

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