Self-timed scan circuit for ASIC fault testing

Electronic digital logic circuitry – Multifunctional or programmable – Having details of setting or programming of interconnections...

Reexamination Certificate

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C326S016000, C714S726000

Reexamination Certificate

active

06972592

ABSTRACT:
A self-timed scan circuit includes a multiplexer for selecting either a data input or a test input in response to an internal test enable signal and for generating a multiplexed output; a latch coupled to the multiplexer for generating a latched output in response to a next clock pulse; and a timing control circuit for generating the internal test enable signal in response to a global test enable signal wherein the internal test enable signal is set to logic one when the global test enable signal is set to logic one and wherein the internal test enable signal is set to logic zero in response to the next clock pulse.

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patent: 2002/0013918 (2002-01-01), Swoboda et al.
patent: 2004/0044937 (2004-03-01), Dubey
patent: 2004/0153801 (2004-08-01), Kayukawa et al.

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