Self-timed redundancy circuit

Details Self-timed redundancy circuit Self-timed redundancy circuit

1994-01-31

1995-10-24

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Bad bit

36523001, G11C 1140

Patent

active

054615860

ABSTRACT:
A circuit for replacing an array element with a redundant element in a semiconductor device is designed with a programmable circuit (128) storing an internal address and coupled to receive a buffered address (120 and 122). The programmable circuit (128) produces first (130) and second (132) redundant addresses in response to the internal and buffered addresses (120 and 122). A first decoder circuit (140), produces a signal to enable the redundant element (142) in response to the first redundant address (130). A second decoder circuit (148) produces a signal to enable the array element (150) in response to the second redundant address (132).

REFERENCES:
patent: 4803656 (1989-02-01), Takemae
patent: 4849939 (1989-07-01), Muranaka et al.
patent: 5208489 (1993-05-01), Houston

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