Self-timed read and write assist and restore circuit

Details Self-timed read and write assist and restore circuit Self-timed read and write assist and restore circuit

2003-10-28

2004-09-07

Yoha, Connie C. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S201000, C365S156000, C365S230060, C365S189011

Reexamination Certificate

active

06788566

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to random access memory technology and architecture, and more particularly to tolerating large threshold voltage fluctuation in memory cells.
2. Description of the Related Art
Large threshold voltage (Vt) fluctuations due to random placement of dopant atoms in small geometry static random access memory (SRAM) cell metal oxide semiconductor field effect transistors (MOSFETs) significantly degrades SRAM array yields in functionality and performance. Presently, there are no known circuit solutions to address this limitation other than brute force reverse scaling of SRAM cell transistor geometries and cell size. One drawback of the reverse scaling approach is that it increases the production cost of the device by increasing die size significantly. Thus, making high performance processors more expensive.
Therefore, a need exists for a structure and method, which counters the negative effects threshold voltage fluctuation in memory cells.
SUMMARY OF THE INVENTION
A read and write assist and restore circuit for a memory device includes a first device, which is responsive to a potential on a bit line such that the potential on the bit line activates the first device. A second device is driven by the first device such that when the first device is activated, a change in the bit line potential is reinforced with positive feedback by the second device during a wordline active period to enable write-back of data lost as a result of threshold voltage fluctuations in memory cell transistors coupled to the bit line.
Another read and write assist and restore circuit for a memory device includes sensing device responsive to a potential on a bit line such that the potential on the bit line activates the sensing device, and a driver device driven by the sensing device such that when the sensing device is activated, a change in the bit line potential is reinforced with positive feedback by the second device during a wordline active period to enable write-back of data lost as a result of threshold voltage fluctuations in memory cell transistors coupled to the bit line. A virtual ground provides a higher potential than a global ground to the memory cell transistors to assist in write operations and during standby.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.


REFERENCES:
patent: 5835429 (1998-11-01), Schwarz
patent: 6314048 (2001-11-01), Ishikawa

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