Self-timed pipelined datapath system and asynchronous signal...

Details Self-timed pipelined datapath system and asynchronous signal... Self-timed pipelined datapath system and asynchronous signal...

2000-09-29

2001-11-20

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S112000, C326S046000

Reexamination Certificate

active

06320418

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a technique in which a multi-threshold CMOS circuit (hereinafter referred to just as a “MT-CMOS circuit”) is applied to a self-timed pipelined datapath system, wherein the MT-CMOS circuit comprises a logic circuit portion formed by a low-threshold CMOS circuit and a power source control circuit composed of high-threshold MOS transistors for supplying electric power to the logic circuit portion, and more particularly to a technique in which the high-threshold MOS transistors composing the power source control circuit in the MT-CMOS circuit are accurately controlled to be on and off along the data flowing order in response to asynchronous signals, thereby to reduce the power dissipation as a whole.
2. Description of the Prior Art
Recently, in view of a magnification of the information to be transmitted and received by portable communication apparatuses, the LSIs installed on them dissipate more power. To address this problem, various techniques for lowering power dissipation have been researched and developed.
Conventionally, an improvement of operating speed of a circuit at a low supply voltage region has been made by a low-threshold CMOS circuit, and a reduction of leakage current in its inactive state has been progressed by high-threshold MOS transistors, whereby a MT-CMOS circuit as a static CMOS circuit capable of realizing both the high-speed operation and low power dissipation has been proposed (S. Mutoh, T. Douseki, T. Aoki, and J. Yamada, “1V-high-speed digital circuit technology with 0.5É m multi-threshold CMOS”, in Proc. IEEE 1993 International ASIC Conf., pp. 186-189, 1993. Or, U.S. Pat. No. 5,486,774.)
FIG. 9A
shows a configuration of a MT-CMOS circuit. In the figure, reference numeral
1
denotes a logic circuit portion (hereinafter it may be referred to just as “logic circuit”) formed by a low-threshold CMOS circuit, to which electric power is supplied from a virtual power rail VDDV and a virtual ground rail GNDV. As shown in
FIG. 9A
, the logic circuit
1
includes a NAND gate composed of low-threshold pMOS transistors MP
1
, MP
2
, low-threshold nMOS transistors MN
1
and MN
2
, and an inverter composed of a low-threshold pMOS transistor MP
3
and a low-threshold nMOS transistor MN
3
.
2
H denotes a circuit for controlling the voltage at the virtual power rail, which is composed of high-threshold pMOS transistors MP
4
and MP
5
, whose sources are connected to the power rail VDD, whose drains are connected to the virtual power rail VDDV, and whose gates are connected to a sleep signal SLP, respectively. Further,
2
L denotes a circuit for controlling the voltage at the virtual ground rail, which is composed of high-threshold nMOS transistors MN
4
and MN
5
, whose sources are connected to the ground rail GND, whose drains are connected to the virtual ground rail GNDV, and whose gates are connected to an inverted sleep signal SLP* (inverted SLP signal), respectively.
In the MT-CMOS circuit, when the sleep signal SLP is “0”, (meaning a low level voltage), and its inverted signal SLP* is “1” (meaning a high level voltage), the high-threshold MOS transistors in the circuit
2
H and in the circuit
2
L are on, the virtual power rail VDDV and the power rail VDD are thereby electrically connected, and the virtual ground rail GNDV and the ground rail GND are also connected respectively, so that the logic circuit
1
is supplied with power and thereby activated. Conversely, when the sleep signal SLP is “1”, and the inverted sleep signal SLP* is “0”, the high-threshold MOS transistors in the circuit
2
H and the circuit
2
L are both off, so that the logic circuit
1
cannot be supplied with electric power, and is put in an inactive state (hereinafter it may referred to just as “sleeping state”).
FIG. 9B
shows an example of the MT-CMOS circuit, which is equivalent to the MT-CMOS circuit of
FIG. 9A
but without the circuit
2
L, and
FIG. 9C
shows an example of the MT-CMOS circuit, which is equivalent to the MT-CMOS circuit of
FIG. 9A
but without the circuit
2
H. In the former MT-CMOS circuit, the logic circuit
1
is controlled to be activated or set to the sleeping state only by the sleep signal SLP, whereas in the latter, the logic circuit
1
is controlled only by the inverted sleep signal SLP*.
On an IC chip as shown in
FIG. 9D
, the MT-CMOS circuit of
FIG. 9A
is preinstalled in the respective blocks
3
through
6
, wherein a circuit block for controlling the power supply
7
generates and sends SLP and/or SLP* signals to each of these blocks
3
through
6
independently. Thus, the activated state and sleeping state of each of the blocks
3
through
6
are controlled independently.
Note that the power source control block
7
may generate only one of the SLP and SLP* signals, and the other signal may be generated within each of the blocks
3
through
6
by way of an inverter. MT-CMOS circuits respectively shown in
FIGS. 9B and 9C
may be used for the blocks
3
through
6
. Further, the SLP and SLP* signals may be supplied externally.
In each block
3
through
6
, when the logic circuit
1
is in the sleeping state, the high-threshold MOS transistors in the respective circuit
2
H and the circuit
2
L are off, the leakage current can be reduced to the level of the high-threshold CMOS circuit, and a reduction of power dissipation is thereby enabled. Further, since the logic circuit
1
is configured by low-threshold MOS transistors only, it performs a high-speed logic operation in its active state even at low supply voltages. In fact, the MT-CMOS circuit features its high-speed operation and its low-level leakage current at low supply voltages. In a conventional CMOS circuit, the leakage current is increased if, for the purpose of accelerating the operating speed thereof, the threshold voltage of the MOS transistors is lowered in compliance with the reduction of the supply voltage, whereas this does not happen to the MT-CMOS circuit.
As mentioned heretofore, it is ensured that the MT-CMOS circuit is effective for reducing the static power dissipation in connection with the low supply voltage. However, basically it is not a circuit for controlling the conductive and/or non-conductive states of the high-threshold MOS transistors therein in accordance with the data flowing order. For this reason, even if it is applied to a pipelined datapath circuit, as long as the high-threshold MOS transistors are on, there still occurs a leakage current even when there is not much data flowing therein, and the static power dissipation is thereby increased.
SUMMARY OF THE INVENTION
The present invention has been achieved to solve the above-described problem and an object of the present invention is to provide a system which controls to make operable only the circuit which is actually in an active state, and reduce the power dissipation in the circuit where no data is being processed when the MT-CMOS circuit is applied to a pipelined datapath circuit.
In order to solve the problems aforementioned, a self-timed pipelined datapath system according to the first embodiment of the present invention is constructed such that it comprises: a pipelined datapath circuit including a plurality of data processing stages, each having a combinational circuit for processing input data, and a register connected to the input side of the combinational circuit; and an asynchronous signal control circuit that controls data transmission to and from each of the registers in the pipelined datapath circuit in response to a request signal; wherein the combinational circuit in each of the plurality of data processing stages is composed of a multi-threshold CMOS circuit, with the multi-threshold CMOS circuit further comprising a logic circuit portion configured by a low-threshold CMOS circuit, and a power control circuit portion, which is configured by a plurality of high-threshold MOS transistors and controls power feeding with respect to the logic circuit portion; and wherein the asynchronous signal control c

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