Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Correction for skew – phase – or rate
Reexamination Certificate
1994-06-17
2001-02-20
Follansbee, John A. (Department: 2783)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Correction for skew, phase, or rate
C710S120000
Reexamination Certificate
active
06192482
ABSTRACT:
DESCRIPTION
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to an improved method and apparatus for transmitting digital data at high speeds via a parallel data bus, and more particularly, to a method and apparatus that provides a cost effective interface to a direct access storage device.
2. Description of the Prior Art
As will be appreciated by those skilled in the art, such factors as noise and loading limit the useful length of parallel busses operating at high data rates. In the prior art, the length of the bus must be taken into account in the system design and the bus length must be precisely as specified. Manufacturing tolerances associated with physical communication link (chips, cables, cord wiring, connectors, etc.) and temperature and variations in power supply voltage also limit the data rates on prior art busses comprised of parallel conductors. Further, many prior art computer systems transfer data synchronously with respect to a processor clock, so that a change in processor clock rate may require a redesign of the data transfer bus.
In a current large computer system, the I/O element can require more than 100 channel functions (as the middle stage/level in a hierarchically arranged busing network) between the highest level internal bus (fastest) and the more numerous and slower I/O controllers. In many system configurations, it is typical for up to 80% of the channels to be used for data transmission paths to the direct access storage device (DASD) data base via DASD I/O controllers. These numerous channels/paths can be required for connectivity to the data base, performance (access rate to the data base) or both.
In prior art systems, the channel's function is to execute, cooperatively with the attached I/O controller, channel programs (lists of channel/controller commands) which have been set up by application or operating system programs in host storage. Typical commands are to initiate the transfer of data between storage and the DASD attached to the I/O controller. Current channel functions are thus designed to transmit this data at a maximum rate (e.g., 18 MB/S) consistent with current DASD I/O controller capabilities.
SUMMARY OF THE INVENTION
An object of this invention is the provision of a cost effective bus data transfer system that can operate at high data transfer rates without tight control of the bus length, and without system clock constraints; a system in which the maximum bus length is limited only by the attenuation loss in the bus.
Another object of the invention is the provision of a general purpose, low cost, high performance, point to point data communication link where the width and speed of the interface can easily be modified to tailor it to specific bandwidth requirements and to specific implementation technologies, including VLSI technologies.
A further object of the invention is the provision of a bus data transfer system that operates a clock rate equal to the data rate.
A more specific object of the invention is the provision of a system that adjusts the phase or arrival time of the incoming data on the receive side so it can be optimally sampled by the local receive clock, compensating for many of the manufacturing tolerances associated with the physical link (chip, cable, card wiring, connectors, etc.) as well as temperature changes and power supply output variations.
Yet another object of the invention is to provide improved, cost-efficient attachment of direct access storage devices (DASD).
DASD I/O controllers can be based on redundant arrays of independent disks (RAID) technology. This significantly increases storage capacity per I/O controller, exceeding the access rate a single channel can support. Many channels are therefore needed per I/O controller. In lieu of using multiple (e.g., 10, 20) channels per I/O controller to match the increased I/O (DASD) controller capability, and still another object of this invention is to reduce the number of links required. A still further object of the invention is to enable channel commands, instead of being forwarded from system port to I/O sub-element channel function and then executed cooperatively by channel function and I/O (DASD) controller, to be forwarded through the I/O sub-element directly to the system DASD I/O controller for execution. Data associated with the commands is routed in the same manner.
Elimination of channel hardware reduces both total system size and cost providing a more effective means for the attachment of local DASD to computer systems.
Briefly, this invention contemplates the provision of a self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individually phase aligned with the clock signal. The received clock signal is used to define boundary edges of a data bit cell. It is defined individually for each line and the data on each line is individually phase adjusted so that, for example, a data transition position is in the center of the defined cell. The data is read into a buffer where it is decoded and read out synchronously with the receiver system clock. At the data rates contemplated in the application of this invention, the propagation delay is significant. However, within limits, the bus length is not critical and is independent of the transmit and received system clock. The phase adjustment can compensate for a skew of up to one bit cell across the width of the bus.
In one specified embodiment of the invention, data to be transmitted is transferred to a buffer synchronously with the transmitter system clock, which may or may not be the receiver system clock. A controller formats the data into packets for byte parallel, bit serial, transmission along with headers specifically coded to provide unique data patterns that allow for correction of skew of up to three bit cells in addition to the initial phase adjustment.
REFERENCES:
patent: 4050097 (1977-09-01), Miu et al.
patent: 4371962 (1983-02-01), Zeitraeg
patent: 4694472 (1987-09-01), Torok et al.
patent: 4771440 (1988-09-01), Fromm et al.
patent: 4791639 (1988-12-01), Afheldt et al.
patent: 4885739 (1989-12-01), Read et al.
patent: 4903258 (1990-02-01), Kuhlmann et al.
patent: 4914429 (1990-04-01), Upp
patent: 5022057 (1991-06-01), Nishi et al.
patent: 5051990 (1991-09-01), Kato
patent: 5113395 (1992-05-01), Murakami et al.
patent: 5113430 (1992-05-01), Richardson, Jr. et al.
patent: 5166926 (1992-11-01), Cisneros et al.
patent: 5237571 (1993-08-01), Cotton et al.
patent: 5251299 (1993-10-01), Masuda et al.
patent: 5410537 (1995-04-01), Niessner
Brady James Thomas
Capowski Robert Stanley
Casper Daniel Francis
Cox Frederick John
Ferraiolo Frank David
Augspurger Lynn L.
Follansbee John A.
International Business Machines - Corporation
Venable
LandOfFree
Self-timed parallel data bus interface to direct storage... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Self-timed parallel data bus interface to direct storage..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Self-timed parallel data bus interface to direct storage... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2567727