Self-timed memory reset circuitry

Details Self-timed memory reset circuitry Self-timed memory reset circuitry

1999-08-17

2001-03-13

Nelms, David (Department: 2818)

Static information storage and retrieval

Addressing

Multiple port access

C365S189040, C365S210130

Reexamination Certificate

active

06201757

ABSTRACT:

BACKGROUND AND SUMMARY OF THE INVENTION
The present application relates to integrated circuit timing architectures, and particularly to memory reset circuitry.
BACKGROUND: DELAYS IN SEMICONDUCTOR CIRCUITS
Integrated circuit fabrication always produces a certain amount of uncontrolled variation in various physical characteristics (such as the thickness of the gate dielectric, the background doping level of the semiconductor surface). Many of these variations cause corresponding variations in the electrical characteristics of the resulting circuits (such as the current drive or switching speed of a minimum-size transistor, or the speed with which a pulse propagates along a minimum-width line). Many of these electrical characteristics will affect the maximum operating speed of the circuit. The maximum operating speed of the circuit will also be affected by external conditions, such as temperature or power supply voltage.
Thus many of the characteristics which limit the maximum operating speed of an integrated circuit are not always easy to predict. However, in many cases timing issues are very important for optimal operation of a circuit.
An example of this is in memory read operations. In the normal read operation of many memories (e.g. high-speed SRAMs), the output of the selected cell is connected to an analog sense amplifier which is in an unstable condition. The sense amplifier includes positive feedback, so that as soon as the selected cell applies even a very small amount of drive to one of the sense amplifier inputs, the sense amplifier will shift all the way to one or the other of its stable states. In this way the analog sense amplifier quickly amplifies the very small signal available from the selected cell. However, timing is important in this operation: if the sense amplifier is enabled too early, it may settle into an unpredictable state (activated by random electrical noise) before the sensed cell can begin to drive the sense amplifier correctly. On the other hand, if the sense amplifier is enabled too late, then the memory will be slower than it might otherwise be.
The delay until the selected cell begins to develop a signal which can correctly drive the sense amplifier is dependent on several factors. Once the address decoder logic has decoded an incoming address and begun to drive the word line, the word line itself imposes a variable delay. (This delay is dependent on the word line's series resistance, and also on the parasitic capacitance seen by the word line.) Similarly, the cell's output drive capabilities are affected by process variations, as is the capacitive (bitline) loading which the selected cell's output must drive. Thus the delay until the sense amplifier can safely be enabled is variable.
As a result of the variability of the array characteristics, engineers traditionally designed arrays timed to the worst possible delay (i.e., what the delay would be if all factors were working against a fast response time). Although this strategy produced reliable arrays, the drawback was that many operations were delayed by the control circuitry well past the point in time at which the array circuitry was effectively settled.
BACKGROUND: THE USE OF DUMMY CELLS IN SELF-TIMED ARRAYS
In order to compensate for fabrication variations and temperature changes in an array, previous designs incorporated “dummy” cells to gauge the time required to read an array cell. The dummy cells are of the same design as the regular memory cells, and should therefore require the same settling time as the regular memory cells. In this scheme, a dummy cell with a certain known state is selected for read at the same time as a regular cell (the state of which is, of course, unknown). At the point in time when the dummy cell returns the proper pre-determined value, the regular cell has settled into a state ready to be read. The scheme works similarly for write operations.
This scheme has several limitations. For one, conventional designs used only a single dummy cell to time the array for both the read and write operations. These designs were inadequate because the dummy cells take the same interval to settle, or to reach a steady voltage, as the regular cells. As a result, the read or write delay is equal to the settling time of the memory cell PLUS the propagation time through the dummy cell feedback circuitry.
The regular core cells are in a state to be accessed even when the voltage in their bitlines is relatively high. (In silicon integrated circuit memories, the bitlines in a memory array normally start high, and are selectively pulled low by an N-channel driver in a selected memory cell.) These voltages are not low enough to drive standard logic gates quickly. Put another way, the cells may be ready to be accessed when their bitlines are at, for instance, 200 mV differential between the complementary bitlines. At this point in time, the voltage across the dummy cells will also be 200 mV. The sense amps connected to the memory array are ready to switch at this differential, but have to wait until the reset signal propagates through the reset circuitry. The propagation time through the feedback circuitry is undesirable extra delay.
With semiconductor memory customers requiring faster and faster arrays, there has been a serious need in the market for self-timing memory circuitry that accurately tracks, without unnecessary delay, the read and write timing of a memory array over a wide range of sizes without redesign.
BACKGROUND: MODULAR MEMORY DESIGN CONSTRAINTS
Memory array design is important far beyond the specific demands of stand-alone memory chips. Modern integrated circuit design often uses libraries of stock design components, such as “standard cells.” The most convenient memory technology for use in conjunction with logic is SRAMs, since (unlike DRAMs or floating-gate memories) SRAM cell technology does not require any nonstandard process steps. Moreover, the peripheral circuitry required to make an array of SRAM cells into a useable embedded memory block are relatively simple, and blocks of SRAM memory can be designed to operate at high speed. This is important when such an embedded memory block is in the critical timing path of a special-function chip.
It would be extremely convenient if designers could easily specify whatever size they wanted for an embedded memory block. However, with present-day technologies memory arrays are not fully modular. This may seem surprising, since the array of memory cells is itself merely a repetitious pattern; but the constraint comes from the peripherals. Conventional array timing circuitry must be optimized for a given array size. Because larger arrays tend to react more slowly to the array circuitry, the timing circuitry was timed to accommodate the largest array conceived of at the time the array control circuitry was designed. The result was that while larger arrays were timed appropriately, smaller arrays were much slower than necessary.
POWER SUPPLY SCALING AND SENSITIVITY
Conventional integrated circuit designs typically specify a reasonably tight constraint on the power supply voltage, e.g. plus or minus ten percent. However, as operating voltages are scaled lower, greater tolerances on supply voltage would be desirable. Moreover, a design which can accept a broad range of supply voltage specifications (with appropriate adjustment of speed and power consumption at different supply voltages) would provide a flexible module which would be very convenient for design libraries and for design automation. In a conventional array design, a small change in voltage can significantly change the timing characteristics of an array. Traditional delay schemes, such as inverter chains, must be completely redesigned for any voltage change in the array.
SELF-TIMED MEMORY RESET CIRCUITRY
The preferred embodiment of the invention disclosed herein uses multiple dummy memory cells to track the timing of at least some memory access operations. During a read operation, the multiple dummy memory cells build up a voltage differential at a f

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