Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
1999-05-05
2001-05-29
Nelms, David (Department: 2818)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S121000
Reexamination Certificate
active
06239622
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to asynchronous circuits, and in particular to an improved asynchronous circuit having zero overhead in forward latency.
Advances in semiconductor fabrication technology continually allow increasing numbers of logic gates to be placed on a single integrated circuit and permit operation of such circuits at speeds greater than prior generations of circuits. Two known methodologies for the design of such circuits are synchronous and asynchronous. Synchronous designs provide a global clock signal which causes all of the circuitry on the integrated circuit chip to operate in lockstep. Asynchronous designs use local control to determine when local gates operate, and the local gates do not necessarily operate in synchrony with the rest of the integrated circuit chip. As such, asynchronous designs eliminate the difficulty of distributing a clock “globally” across the integrated circuit, and also potentially offer improved speed, lower power consumption, and other benefits.
Asynchronous circuits can be broadly characterized as self-timed and timed. Self-timed asynchronous circuits, often referred to as delay insensitive circuits, use a “hand shake” between data and control circuits to assure that the control does not request operations until the appropriate data is available. Timed circuits attempt to match the delays of the control and data circuits so that the control circuit does not activate until the data is ready. As a result, self-timed circuits are more robust because they do not depend upon accurate matching of delays, a difficult phenomenon over the wide range of performance resulting from tolerances in integrated circuit manufacturing processes. In self-timed circuits, the data signals indicate not only the value of the data, but also its validity. This enables the control system to assure data validity before processing the data. One technique for achieving this is to encode a data bit using two signals, referred to as dual rail signaling. If both signals are low, the data is invalid. If the first signal is high and the second low, the data can be considered high, while if the second is high and the first low, the data can be considered low. A condition of both signals being high is not permitted.
Prior self-timed domino circuits are generally discussed and disclosed in a commonly assigned copending patent application “Apparatus and Methods for High Throughput Self-Timed Domino Circuits,” Ser. No. 09/305,904, filed May 5, 1999 by David Harris and William Coates.
SUMMARY OF THE INVENTION
This invention provides a new domino control circuit which provides delay insensitive characteristics of self-timed circuits. In addition, it provides improved cycle time and zero overhead latency. In a preferred embodiment of the invention, a method of controlling a data path having a plurality of stages is provided. The data path includes sequential stages i−1, i and i+1, each of which performs a logic function on input signals supplied to it, and each stage requires a first time period for precharging and a second time for evaluating. The method includes the steps of evaluating the logic function of the stage i when stage i+1 is precharging, and precharging stage i when stage i+1 has completed evaluating, but before stage i+1 begins precharging, and when stage i−1 has completed precharging.
Furthermore, in a preferred embodiment, the circuit for use in the self-timed system having a sequence of stages i, i−1 and i+1 in which request and done signals are exchanged between a control path and a data path includes a series of four sequentially connected transistors connected between a first source of high potential and a second source of low potential, with the first transistor connected to the high potential and the fourth transistor connected to the low potential. An output signal is taken from between the third and the fourth transistor. In such a circuit, the first, second and third transistors are controlled by a request signal for the i+1 stage, a done signal from the i−1 stage, and a done signal from the i+1 stage. The fourth transistor is controlled by a request signal for the i+1 stage.
REFERENCES:
patent: 5541537 (1996-07-01), Kim et al.
patent: 5828234 (1998-10-01), Spargue
patent: 5973529 (1999-10-01), Chappell et al.
Le Thong
Nelms David
Sun Microsystems Inc.
Townsend and Townsend / and Crew LLP
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