Self-timed data amplifier and method for an integrated circuit m

Details Self-timed data amplifier and method for an integrated circuit m Self-timed data amplifier and method for an integrated circuit m

2000-03-21

2000-12-12

Phan, Trong

Static information storage and retrieval

Read/write circuit

For complementary information

365207, G11C 700

Patent

active

061607436

ABSTRACT:
A self-timed data amplifier and method for an integrated circuit memory device which overcomes the power consumption problems of conventional static data amplifiers while providing a high speed amplification function within design margins. By self-timing the un-equilibration of the data lines ("DQ" and its complement "DQB"), powering the main data amplifier and latching its output all with the same clock that controls the column address for the device, a high speed, low power, low risk approach is achieved. In a particular embodiment of the present invention, this may be effectuated by the integration of an amplifying, latching and equilibration function wherein all of the related circuitry is controlled by the memory device Y-clock signal (YCLKB) and the write signal (WRITEB) signal. In operation, the YCLKB signal goes "low" when a column address is determined to be valid, which then allows the DQ and DQB lines to be driven. The WRITEB signal goes "low" when a write command is asserted to the memory device keeping the differential amplifiers "off" in order to conserve power.

REFERENCES:
patent: 4623989 (1986-11-01), Blake
patent: 4791613 (1988-12-01), Hardee
patent: 5986955 (1999-11-01), Siek et al.
patent: 6005816 (1999-12-01), Manning et al.

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