Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Patent
1995-08-21
1996-10-15
Westin, Edward P.
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
326 17, 326 21, 326 40, H03K 1900
Patent
active
055657982
ABSTRACT:
A self-timed control circuit for self-resetting CMOS logic circuitry provides handshaking between macros to ensure that all data inputted to a particular macro is maintained by the source macros until all data inputs have been received. A data output signal from a macro is maintained until the macro receives a complete signal from all receiving macros indicating that the receiving macros have received all data inputs supplied to them.
REFERENCES:
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patent: 5373204 (1994-12-01), Muramatsu
patent: 5434519 (1995-07-01), Trinh et al.
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United States Patent Application Serial No. 08/450,056.
United States Patent Application Serial No. 08/461,961.
Durham Christopher M.
Klim Peter J.
International Business Machines - Corporation
Kordzik Kelly K.
McBurney Mark E.
Sanders Andrew
Westin Edward P.
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