Self-timed CMOS static logic circuit

Details Self-timed CMOS static logic circuit Self-timed CMOS static logic circuit

1998-04-27

2003-02-18

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S096000

Reexamination Certificate

active

06522170

ABSTRACT:

TECHNICAL FIELD
The present invention relates in general to logic circuitry, and in particular, to self-timed logic circuitry.
BACKGROUND INFORMATION
Self-timed circuit techniques, once thought only as research-oriented projects, are quickly becoming mainstream in VLSI circuit applications. Requiring no clocks for operation, as does a traditional system, self-timed circuits operate asynchronously on the simple concept of demand. That is, a self-timed circuit operates only when asked to, generates the necessary outputs according to its own internal scheduling, and presents the results to the requester. Afterwards, the circuit “goes to sleep” and awaits the next instruction/request. While asleep, no power is dissipated since no operation is taking place.
This is contrary to traditional synchronous systems where even when a circuit is not needed, there is at least power dissipated by the clock circuitry running through the system. This idle power can be significant—studies show that clocking power is approximately 30% of the overall power on a given VLSI circuit/chip. Consequently, self-timed circuits have at least a power advantage over traditional methods.
Self-timed circuits also have significant advantages over other techniques such as self-resetting. This approach requires no interaction between driving and receiving circuitry, creating scheduling and arrival time conflicts and complications.
FIG. 1
shows an example of a self-timed logic circuit pipeline, or unit
100
. Note in
FIG. 1
that each block
101
-
104
labelled “Self-timed Logic Circuit” can, itself, be a combination of self-timed circuits.
The operation of such a self-timed system is straightforward and is presented briefly below. Note that this example is an extremely small system. Also, note that each sub-block
101
-
104
labelled in
FIG. 1
as a “Self-Timed Logic Circuit” may, itself, contain multiple self-timed circuit stages and, thus, may also contain operation internally as described below:
The input source(s) indicates to the Self-Timed Logical Unit
100
by asserting the “request” signal and enabling the “data inputs” (a bus or multiple of bus signals). Note that the number of such sources is not limited to one, but is only shown as one in
FIG. 1
for simplicity.
The first (receiving) Self-Timed Logic Circuit “a”
101
notes that a “request” has been made and returns the “acknowledge” signal to the source(s). This signifies to the sources that the information on the “data inputs” has been received. The logic (not shown) that drives the source signals (“data inputs”) is now free to de-assert the “data inputs”, do other operations, etc., since the Self-Timed Logical Circuit “a”
101
has received the input information and has begun operating.
Self-Timed Logic Circuit “a”
101
operates on the “data inputs” and produces a “valid output signal” to Self-Timed Logic Circuits “b”
102
and “c”
103
along with “data output signals”. Circuits “b”
102
and “c”
103
receive the information and send “complete out” signals back to circuit “a”
101
to signify capture of the incoming information. Circuit “a”
101
is now free to de-assert the output information and, if necessary, receive further inputs from the logical unit input sources.
Self-Timed Logic Circuits “b”
102
and “c”
103
operate on the input information and produce “valid output signals” and “data output signals”, which are then sent to Self-Timed Logic Circuit “d”
104
.
Circuit “d”
104
awaits for both “valid signals” to arrive, then returns a “complete out” signal back to both circuits “b”
102
and “c”
103
. Circuits “b”
102
and “c”
103
are now able to de-assert their respective outputs and receive further information as necessary from circuit “a”
101
.
Self-Timed Logic Circuit “d”
104
operates on the information and produces a “valid output signal” and “data output signals” to the external sink (not shown) in the overall chip system. Note that sinks (not shown) may be single or multiple, depending on the particular architecture and placement of a self-timed logical unit. When, the receiving units (sinks) signify that the information has been received (via “completion signals from sinks”) the Self-Timed Logic Circuit “d”
104
may de-assert its outputs and receive further information from circuits “b”
102
and “c”
103
.
To control this operation, please refer to U.S. Pat. Nos. 5,565,798 and 5,708,374, which are hereby incorporated by reference herein.
As a result of this operation, it can be seen that in the general self-timed case, no registers are required. That is, in a completely self-timed system, the combination of valid/complete cycles removes the necessity of synchronization of internal units and sub-blocks as the units, in reality, time and clock themselves. Thus, self-timed circuits and systems synchronize themselves. Therefore, in the limit, a completely self-timed microprocessor, for example, would require no on-chip or off-chip clocks.
However, most self-timed circuitry is dynamic. As such, it is prone to errors created by noise events, as are all dynamic circuits, and, additionally, must distribute the self-timing clocks to every circuit. For example, consider the circuits of
FIGS. 2A
,
2
B, and
2
C, which were described in U.S. Pat. Nos. 5,565,798 and 5,708,374. (Some signals are not shown in
FIG. 2A
to reduce complexity and increase understanding of the present invention.) In this circuitry, each “Domino Logic Row” of the “Self-Timed Macro Dataflow” in
FIG. 2C
receives a clock signal (“Strobe” or “Reset”) from the control circuit in FIG.
2
B. Note that each “Domino Logic Row” is constructed of a collection of domino circuits.
One drawback of such a system is in the use of the dynamic circuits for all functions. That is, dynamic circuits are susceptible to noise events, which cause them to evaluate improperly and from which they cannot recover; they require a clock signal to be routed to each circuit, which increases the design complexity and the chip clocking loading; they create more on-chip noise due to precharge/evaluate events, fast edge rates, and the multitude of clock signals (noise coupling to adjacent lines); they cause test problems, particularly at elevated temperatures and voltages, much of which is necessary for reliability and screening; and they must wait upon the clock signal in order to start the evaluation process, which makes them susceptible to clock skew problems.
Static circuits, on the other hand, do not suffer from many of these issues: they can always recover from an incorrect evaluation, given enough time, and, consequently and importantly, a correct state can always be gained by waiting; they require no clock signals, which reduces the design complexity and global chip clock loading; they tend to reduce the overall chip noise as the precharge/evaluate nature is removed and the clock signals are not required; they are “friendly” to test at elevated temperatures and voltages as functionality is nearly always guaranteed; and they do not need to wait upon a clock signal for evaluation as one is not required. Also, they typically dissipate less power than their dynamic counterparts, mainly due to the removal of the clock signal to each circuit, which requires a switching clock signal every cycle regardless of the switching activity of the dynamic circuit. Examples of static circuits are illustrated in
FIGS. 11A and 11B
.
An important key, however, is performance. Dynamic circuits, with all their hazards and complications, consistently outperform static circuits in terms of delay. This means that critical circuit paths tend to be dynamic to produce the fastest chip possible, while non-critical circuit paths tend to be static to reduce power and design hazard as the performance is not critical (the chip (clock) speed is always set speed by the slowest possible path). In typical clock systems, this is not an issue as the latch boundaries separate the circuit styles, permitting static and dynamic circuits to coexist. This means, generally, that static and dynamic circuits can, effecti

Affiliated with

Also associated with

Rating

Self-timed CMOS static logic circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Self-timed CMOS static logic circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Self-timed CMOS static logic circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3120297