Self-timed clocking transfer control circuit

Details Self-timed clocking transfer control circuit Self-timed clocking transfer control circuit

1993-08-31

1994-12-13

Hudspeth, David R.

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

377 81, 326 21, H03K 19096

Patent

active

053732049

ABSTRACT:
A self-timed clocking transfer control circuit includes a flipflop for storing a transition of a transfer request signal to an L level and outputting an H level signal, an inverter for applying a transfer acknowledge signal to a preceding stage, a 5-input NAND gate, and a second signal output circuit for applying a transfer request signal to a succeeding stage in response to a transition of the output of the 5-input NAND gate to the L level. The 5-input NAND gate does not output the L level unless the transfer request signal from the preceding stage, the output of the flipflop, the transfer acknowledge signal from the succeeding stage, the transfer request signal output by the self-timed clocking transfer control circuit itself, and the prohibition signal are all in the H level. Setting the prohibition signal to the L level, self-synchronous type transfer control can be prohibited. A circuit for generating such a prohibition signal based on a signal for setting an operational mode, a clock signal, and the transfer request signal from the preceding stage may additionally be provided.

REFERENCES:
patent: 4679213 (1987-07-01), Sutherland
patent: 4995003 (1991-02-01), Watanabe et al.
patent: 5003201 (1991-03-01), Bai
patent: 5067069 (1991-11-01), Fite et al.
patent: 5109495 (1992-04-01), Fite et al.
patent: 5128974 (1992-07-01), Maekawa
patent: 5221866 (1993-06-01), Takatsu

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