Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2000-09-27
2001-08-28
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Signals
C365S233100, C365S230030
Reexamination Certificate
active
06282131
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates generally to high-speed semiconductor memories. More particularly, and not by way of any limitation, the present invention is directed to compilable memory instances having self-timed clock circuitry for synchronizing a falling edge of a signal immediately derived from an external master clock to a falling edge of a common node signal driven by a selected bank in a multi-bank memory architecture.
2. Description of Related Art
Design re-use has emerged as a key solution for successfully addressing the time-to-market problem in semiconductor IC design. In this paradigm, instead of re-designing every part of every IC chip, engineers can re-use existing designs as much as possible and thus minimize the amount of new circuitry that must be created from scratch. It is commonly accepted in the semiconductor industry that one of the most prevalent and promising methods of design re-use is through what are known as Intellectual Property (“IP”) components—pre-implemented, re-usable modules of circuitry that can be quickly inserted and verified to create a single-chip system (system-on-chip or SOC). Such re-usable IP components are typically provided as megacells, cores, macros, embedded memories through generators or memory compilers, et cetera.
It is well known that memory is a key technology driver for SOC design. It is also well known that robust performance of memory is pivotal, whether provided in an embedded SOC application or as a stand-alone device. For high speed and high density memories, accordingly, it is desirable that memory access operations are performed without any glitches on the selected wordlines, because such glitches on the wordlines could corrupt data. Further, it is highly desirable for a compiled memory instance to operate with very relaxed requirements on the input clock duty cycle.
One scenario where a wordline (WL) glitch may be encountered is when the falling edge of an external input clock is used to enable the inputting of address information in a multi-bank memory instance, wherein the external clock has a short duty cycle (i.e., short high time). Thus, it is possible that a new address (or an intermediate address if not all predecoders have the same delay) can arrive before the access in a selected memory bank is completed. Consequently, such “early” address signals can glitch the wordline to the new address near the end of the access cycle (which can be a significant problem particularly during a write cycle, where data stored could be corrupted by a false glitch on an unselected WL).
It is therefore highly desirable to have a more or less self-contained timing chain in each bank in a multi-bank memory architecture. Accordingly, a feedback must come from the bank timing chain to a master clock buffer to delay the inputting of the new address and control information into the memory instance until the present memory operation is complete.
SUMMARY OF THE INVENTION
The present invention addresses the requirements with respect to an input clock's short high time (duty cycle) by advantageously providing a self-timed clock circuitry for use in a compilable memory instance using a common timing synchronization node, wherein address input operations of the memory instance for the subsequent cycle are synchronized to arrive after completion of memory access operations. A plurality of memory banks are provided in the memory instance wherein each memory bank is independently selectable by a bank select (BS) signal generated by a global control circuit. A global timing circuit is provided to drive the common timing synchronization node, hereinafter referred to as DBITFB, to a high value upon application of the rising edge of an external master clock and a memory enable signal to the memory instance. The global timing circuit is operable to drive the common node DBITFB signal high for a predetermined time period using a one-shot circuit with programmable delay. A local driver circuit associated with a particular memory bank selected by a specific BS signal takes control of driving the common node DBITFB signal thereafter so as to maintain its high state. It is highly desirable for such a common feedback node to be controllable by both the selected bank as well as the global input clock circuitry, without contention between the two controlling units, and also without the common line floating for any period of time, where it may become susceptible to coupling from a long parallel line which could cause a failing glitch in the common line.
Based upon the specific BS signal (which acts as the “master” clock for the local memory bank), a local clock generator circuit associated with the selected memory bank generates a local wordline clock (LWC) by further decoding a plurality of global wordline clock (GWC) signals to synchronize a memory access operation with respect to a memory location of the selected bank. The LWC signal is also used for synchronizing a dummy access operation involving a dummy memory cell (by way of activating a particular dummy wordline (DWL)), wherein the dummy access operation has substantially the same timing delay as the actual memory access operation. A dummy bitline (DBL) signal is generated upon completing the access operation's timing path and is driven low for firing sense amp circuitry and to enable the shut down of the DWL through LWC signal. A reference signal (SD_CLK) derived from the activation in the negative direction of the DBL signal is subsequently driven low. Thereafter, the falling edge in the reference signal SD_CLK drives the local driver circuit to drive the common node DBITFB signal low. The global timing circuit then continues to drive the common node signal low, until a rising edge of the external clock signal (indicating the beginning of a new memory cycle) has been encountered. The low state of the common node signal opens the input latches for incoming address information for the next memory access operation.
In an exemplary embodiment, the one-shot circuit in the one-time global clock circuitry comprises a plurality of inverters coupled in series wherein the programmable delay portion is operable to provide variable time periods for which the common node DBITFB signal is driven high by the global timing circuit, based on the number of banks in the memory instance. Such variable time periods advantageously accommodate multi-bank memory instances of different heights in a compilable architecture.
In another aspect, the present invention is directed to a timing synchronization method with respect to a memory access operation for synchronizing a falling edge of a signal (referred to as the primary internal clock) derived from an external master clock signal to a falling edge of a common node signal internal to a memory instance having a plurality of banks, in order to guarantee that the internal access has been completed prior to the introduction of new address information into the memory instance. Upon application of the external master clock and memory enable signals to the memory instance, the common node DBITFB signal is driven high for a predetermined time period by a global clock circuit disposed in the memory instance. A particular bank of the memory instance is selected for the memory access operation by asserting a BS signal associated therewith. The common node DBITFB signal is held high by a local driver circuit associated with the local clock generator circuit that is provided for the selected bank. By further decoding a plurality of GWC signals using the BS signal, the local clock generator circuit generates an LWC signal for synchronizing the memory and dummy access operations. Upon completing the access timing path, a DBL signal is driven low which, in turn, drives a reference signal SD_CLK low. The local driver circuit then drives the common node DBITFB signal low. If the falling edge of the external master clock occurs prior to the local driver circuit driving the common node DBITFB signal low, it will b
Nguyen Tan T.
Smith ,Danamraj & Youst, P.C.
Virage Logic Corp.
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