Self-timed carry look-ahead adder and summation method thereof

Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed

Reexamination Certificate

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C708S714000

Reexamination Certificate

active

07424508

ABSTRACT:
A carry look-ahead adder may include: a carry generation circuit to generate carry propagation bit values and carry kill bit values for M blocks based on an N-bit addend and augend; a block carry circuit to generate block carry signals based upon the bit values; a Manchester-carry-chain configured bit carry circuit to generate first bit carry signals where a block carry exists in each of the M blocks and second carry bit signals where no block carry exists, based on the bit values; a control circuit to generate, independently of a clock enable signal at a logical level, selection-control signals based upon the block carry signals; and a summation selection circuit to select between the first bit carry signals and the second bit carry signals and to add the carry propagation bit values and the selected carry signals.

REFERENCES:
patent: 5136539 (1992-08-01), Kumar
patent: 5487025 (1996-01-01), Partovi et al.
patent: 5508952 (1996-04-01), Kantabutra
patent: 6012079 (2000-01-01), Song
patent: 6742014 (2004-05-01), Bradley
patent: 6839729 (2005-01-01), Pham
patent: 2002/0143841 (2002-10-01), Farooqui et al.
patent: 1993-61643 (1993-03-01), None

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