Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2002-07-31
2003-11-04
Phung, Anh (Department: 2824)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S189040
Reexamination Certificate
active
06643204
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
This invention relates to semiconductor memory and, more particularly, to performance enhancement of semiconductor memory by using a self-time mechanism to selectively reduce a write interval and power consumption associated therewith.
2. Description of Related Art
Semiconductor memory is a crucial resource in modern computers, being used for data storage and program execution. With the exception of the central processor itself, no other component within the computer experiences as high a level of activity. Traditional trends in memory technology are toward greater density (more memory locations, or “cells,” per memory device), higher speed and improved efficiency. To some extent, these goals are inconsistent. For example, as memory speed increases, power consumption generally also rises.
There are various types of semiconductor memory, including Read Only Memory (ROM) and Random Access Memory (RAM). ROM is typically used where instructions or data must not be modified, while RAM is used to store instructions or data which must not only be read, but modified. ROM is a form of non-volatile storage—i.e., the information stored in ROM persists even after power is removed from the memory. On the other hand, RAM storage is generally volatile, and must remain powered-up in order to preserve its contents.
A conventional semiconductor memory device stores information digitally, in the form of bits (i.e., binary digits). The memory is typically organized as a matrix or array of memory cells, each of which is capable of storing one bit. The cells of the memory matrix are accessed by word lines and bit lines. Word lines are typically associated with the rows of the memory matrix, and bit lines with the columns. Raising a word line activates a given row; the bit lines are then used to read from or write to the corresponding cells in the currently active row. Memory cells are typically capable of assuming one of two voltage states (commonly described as “on” or “off”). Information is stored in the memory by setting each cell in the appropriate logic state. For example, to store a bit having the value 1 in a particular cell, one would select the cell by activating the appropriate bit line and word line and then set the state of that cell to “on;” similarly, a 0 would be stored by setting the selected cell to the “off” state. Obviously, the association of “on” with 1 and “off” with 0 is arbitrary, and could be reversed.
The two major types of semiconductor RAM, Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM), differ in the manner by which their cells represent the state of a bit. In an SRAM, each memory cell includes transistor-based circuitry that implements a bi-stable latch. A bi-stable latch relies on transistor gain and positive (i.e. reinforcing) feedback to guarantee that it can only assume one of two states—“on” or “off”. The latch is stable in either state (hence, the term “bi-stable”). It can be induced to change from one state to the other only through the application of an external stimulus. Left undisturbed, it will remain in its original state indefinitely. This is just the sort of operation required for an SRAM memory circuit, since once a bit value has been written to the memory cell, it will be retained until it is deliberately changed. Each memory cell may be accessed using a pair of complementary bit lines. The bit lines are driven, to write a new value into the cell, or read by a sense amplifier, to read out the current value. Prior to each access, the bit lines must be pre-charged to a prescribed logic level.
The entire time interval required to complete a read or write operation to an SRAM memory cell is termed the read/write cycle time. The read cycle time has two components; a read access interval and a read pre-charge interval. During the read access interval, the logic state of the cell is acquired by the associated sense amplifier. The pre-charge interval immediately follows the read access. During the pre-charge interval, the bit lines associated with the cell are pre-charged to prepare for the next read cycle. Similarly, a write cycle consists of a write access interval (during which the input data is transferred into the memory cell), followed by a write pre-charge interval. For most SRAM memory devices, the read and write cycle times are not equal. The read access time is typically longer than the write access time, while the write pre-charge time is generally longer than the read pre-charge time.
In contrast to the SRAM, the memory cells of a DRAM employ a capacitor to store the “on”/“off” voltage state representing the bit. A transistor-based buffer drives the capacitor. The buffer quickly charges or discharges the capacitor to change the state of the memory cell, and is then disconnected. The capacitor then temporarily holds the charge placed on it by the buffer and retains the stored voltage level.
DRAMs have at least two drawbacks compared to SRAMs. The first of these is that leakage currents within the semiconductor memory are unavoidable, and act to limit the length of time the memory cell capacitors can hold their charge. Consequently, DRAMs typically require a periodic refresh cycle to restore sagging capacitor voltage levels. Otherwise, the capacitive memory cells would not maintain their contents. Secondly, changing the state of a DRAM memory cell requires charging or discharging the cell capacitor. The time required to do this depends on the amount of current the transistor-based buffer can source or sink, but generally cannot be done as quickly as a bistable latch can change state. Therefore, DRAMs are typically slower than SRAMs. DRAMs offset these disadvantages by offering higher memory cell densities, since the capacitive memory cells are intrinsically smaller than the transistor-based latching cells of an SRAM.
SRAMs are widely used in applications where speed is of primary importance, such as the cache memory typically placed proximate to the processor or Central Processing Unit (CPU) in a personal computer. However, the timing of its internal circuitry may critically affect the speed and efficiency of the SRAM. For example, the bit line pre-charge interval comprises an appreciable portion of the read/write cycle time, and sense amplifier usage contributes significantly to the overall power consumption of the SRAM. In early SRAM memory designs, all read/write cycle timing was based on an externally generated clock signal. For example, if the SRAM were used in a microcomputer, the bus clock in the memory interface would determine the read/write timing characteristics of the SRAM.
Though conceptually simple, reliance on the bus clock results in excessive power consumption. One reason for this is that the sense amplifiers used to read the contents of each SRAM memory cell consume significant power while they are active. In the original approach described above, the sense amplifiers would remain active until the end of a memory cycle, as determined by the externally generated clock. In many cases, the sense amplifier would have completed its access of the respective cell before the end of the cycle, and would thus be maintained in an active state (consuming power) throughout a portion of the cycle when it was not serving any useful purpose.
To overcome the inefficiency of the above-described approach, SRAM manufacturers incorporated “self-time” circuitry into the internal SRAM circuitry, to control timing independently of the externally generated clock signal. The self-time circuitry establishes the interval allowed for reading or writing the contents of the memory locations, together with the subsequent pre-charge interval.
While this use of self-time circuitry improves efficiency, it is not an optimal solution. For simplicity, existing self-time schemes assign the same access and pre-charge times for both read and write memory accesses. Actually, this is a misrepresentation, since write access times are typically shorter than read access times, and write pre-charge tim
Conley Rose & Tayon
LSI Logic Corporation
Phung Anh
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