Self-testing circuit in semiconductor memory device

Details Self-testing circuit in semiconductor memory device Self-testing circuit in semiconductor memory device

2007-01-30

2007-01-30

Baderman, Scott (Department: 2114)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S711000, C714S723000

Reexamination Certificate

active

10360862

ABSTRACT:
A semiconductor memory device includes a self-testing circuit and a self-redundancy circuit with simple structures. The self-testing circuit includes a comparison circuit which compares write data with read data with respect to normal memory blocks and redundant memory blocks, and a decision circuit which decides if the semiconductor memory device is good or defective based on the plurality of comparison result signals. A signal transfer and holding circuit is connected between the comparison circuit and the decision circuit to transfer the plurality of comparison result signals to the decision circuit and to supply the plurality of comparison result signals to the self-redundancy circuit as a test result.

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