Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Patent
1995-10-06
1999-07-20
Chung, Phung M.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
714718, G11C 2900
Patent
active
059251425
ABSTRACT:
A semiconductor memory device is disclosed that can be operated in a speed test mode. The memory device includes an array of memory cells capable of storing data, a control circuit receiving a signal from an external system clock and controlling data transfer operations between the memory device and an external data bus, and a test mode circuit receiving the external clock signal. When operated in speed test mode, the control circuit provides a signal to the test mode circuit enabling its function. A predetermined data pattern is first written to one or more cells, and then subsequently accessed during a read cycle. The enabled test mode circuit compares the contents of an internal data bus to the predetermined data pattern at a time referenced to the system clock signal. In the case of a failed comparison, the test mode circuit produces a signal that places the external data bus in a high impedance state. The disclosed memory device is therefore capable of itself providing some of the test functions previously provided by external testing equipment, and speed testing equipment in particular.
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Pinney David L.
Raad George B.
Chung Phung M.
Micro)n Technology, Inc.
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