Static information storage and retrieval – Read/write circuit – Testing
Patent
1997-04-22
1999-06-08
Fears, Terrell W.
Static information storage and retrieval
Read/write circuit
Testing
365200, G11C 1300
Patent
active
059109211
ABSTRACT:
DRAM self-test circuitry, when triggered by an external signal, performs an on-chip test of a DRAM memory array. The self-test circuitry writes either all ones or all zeroes to each set of physical rows having the same address within the segment to be tested, and then reads the rows a set at a time. If the data bits comprising the set do not all equal one or zero, a resultant error detection signal is generated and used to latch the failed addresses into a failed address queue. If the data bits are either all zeros or ones, the next set of rows are tested. When the self-test is complete, the failed addresses stored in the queue may be transmitted to an external, off-chip device or analyzed and acted on by on-chip error correction circuitry. The self-test circuitry further includes circuitry to detect data bit transitions between successive failing addresses latched in a the address queue. If the transition circuitry determines that one or more bits have the same logic in all of the failed addresses, a partialing technique may be employed to repair DRAMs that have more failing rows/columns than redundant rows/columns.
REFERENCES:
patent: 5668763 (1997-09-01), Fujioka et al.
patent: 5751647 (1998-05-01), O'Toole
patent: 5754484 (1998-05-01), Perreault
patent: 5757716 (1998-05-01), Lee
patent: 5761138 (1998-06-01), Lee et al.
Beffa Ray J.
Cloud Eugene H.
Farnworth Warren M.
Nevill Leland R.
Waller William K.
Fears Terrell W.
Micro)n Technology, Inc.
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