Self-test of a memory device

Details Self-test of a memory device Self-test of a memory device

1998-07-31

2000-09-12

Nguyen, Hoa T.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

365201, G01R 3128

Patent

active

061192511

ABSTRACT:
DRAM self-test circuitry performs an on-chip test of a DRAM memory array. The self-test circuitry writes either all ones or all zeroes to each set of physical rows having the same address within the segment to be tested, and then reads the rows a set at a time. If the data bits comprising the set do not all equal one or zero, a resultant error detection signal is generated and used to latch the failed addresses into a failed address queue. If the data bits are either all zeros or ones, the next set of rows are tested. In another embodiment, the self-test circuitry also includes a mechanism for determining the performance of the addressed memory with respect to speed as well as accuracy. When either self-test is complete, the failed addresses stored in the queue may be transmitted to an external, off-chip device or analyzed and acted on by on-chip error correction circuitry. The self-test circuitry further includes circuitry to detect data bit transitions between successive failing addresses latched in a the address queue. If the transition circuitry determines that one or more bits have the same logic in all of the failed addresses, a partialing technique may be employed to repair DRAMs that have more failing rows/columns than redundant rows/columns.

REFERENCES:
patent: 4875210 (1989-10-01), Russo et al.
patent: 5515323 (1996-05-01), Yamazaki et al.
patent: 5606370 (1997-02-01), Moon

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