Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2001-11-13
2003-12-02
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
With measuring or testing
C716S030000, C716S030000, C716S030000, C716S030000, C714S030000, C714S721000, C714S733000, C365S201000
Reexamination Certificate
active
06656751
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
This invention generally relates to semiconductor devices, and more specifically relates to self-test devices for memory arrays.
2. Background Art
The proliferation of modern electronics is due in large part to the development of the integrated circuit (IC). IC designs are implemented on a silicon die by mapping logic functions to a set of pre-designed, pre-verified logic circuits. These circuits range from the simplest functions to highly complex circuits referred to as “cores.” Cores are typically high level industry-standard functions, such as a digital signal processor (DSP), an advanced RISC machines (ARM) microprocessor, an Ethernet function, or a peripheral component interconnect (PCI) controller. With a particular design in mind, customers can quickly assemble an application specific IC, or ASIC, design by using cores as building blocks.
One of the more commonly used cores are those that provide memory arrays for use in ASICs. Typically, memory cores are designed to be compilable, i.e., the parameters of the memory array can be customized to meet the requirements of a particular design. Typically, a compilable memory core allows the design to specify parameters such as the number of words and the width of the words. Additionally, compilable memory array cores typically allow designers to specify decode options and other parameters. Thus, one ASIC memory array core can provide memory structures for a wide variety of applications.
Modern memory arrays commonly include self-test circuitry designed to facilitate testing of the memory array after fabrication. These devices, typically referred to as “built-in-self-test” (BIST) controllers, provide the memory core with the ability to perform self tests to determine which cells in the memory are functioning properly. Typically, these BIST controllers provide the ability to perform a test pattern routing that involves writing to each memory cell in the array, and then reading from the cells to determine which cells are operating properly. In particular, the BIST controller writes a defined pattern into the memory, and reads the data back from the array. The read data is then compared to the “expect data” by a self test comparator within the memory array, and the memory sends back a pass/fail signal. The BIST then logs the pass/fail, and uses that information to determine whether the memories embedded within the ASIC are functional.
Memory arrays have many applications, and come in many forms. In order to accommodate a maximum number of users, some memory arrays, such as SRAM designs, are required to operate over a wide range of power and temperature conditions. A robust testing procedure for this and other memory arrays includes test coverage through Level Sensitive Scan Design (LSSD), Extended Voltage Screen (EVS), and Dynamic Voltage Screen (DVS). In order for SRAM designs to be tested at DVS they must be fully functional up to voltages much higher than those used during normal operation. The intent of the DVS test is to find resistive-type defects that do not necessarily cause a “hard” struck-type fail. This type of fail is sensitive to the higher power supply during the DVS test, and the slower timing utilized is not significant relative to AC defects. The integrity of the DVS test is, therefore, preserved.
Existing self test methods and devices are flawed in that they require that critical timing elements be tuned to be slower than might otherwise be needed to ensure that data is written and read during DVS test. This compensates for the speed up effects at higher voltage, thus avoiding undesirable race conditions that would render the memory array inoperable. This extra delay, added for the sole purpose of making the design functional at DVS test conditions, becomes more pronounced at normal and low operating voltages, which translates to much slower functional memory access and cycle times.
SUMMARY OF THE INVENTION
Therefore, there exists a need for a self test method and apparatus capable of optimum functionality both at DVS test and normal operating conditions. The present invention fills that need by providing a device that includes a built-in-self-test controller having a mechanism for providing an interface signal that indicates whether a DVS test is being performed. The self-test controller is associated with a memory array that includes a clock having a clock speed. The memory array also includes a clock adjuster that receives the interface signal and reduces the clock speed when the interface signal indicates that a DVS test is being performed.
This configuration provides tester control for a new capability which is provided to the memory array designer. Specifically, it allows the selection within the array of a slower clock delay or modified internal clock waveform during DVS, such that two timings are available. The normal (faster) array timing can be tuned to function at the conditions that a customer would use. For DVS test, the slower timing may be used. This would allow additional delay or a modified pulse to be selected, allowing the array to be functional at DVS conditions. With this approach, a performance advantage in smaller delays and cycle time is realized for the user since it is not necessary to add additional delay for functional mode.
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Andersen John E.
Cowan Bruce M.
Gillis Pamela S.
Oakland Steven F.
Ouellette Michael R.
Lee Jr. Granvill D
Schmeiser Olsen & Watts
Smith Matthew
Walsh Robert A.
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