Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2008-04-29
2008-04-29
McCarthy, Christopher (Department: 2113)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S733000
Reexamination Certificate
active
11008371
ABSTRACT:
A computing system is provided which includes a processor having a cache memory. The cache memory includes a plurality of independently configurable subdivisions, each subdivision including a memory array. A service element (SE) of the computing system is operable to cause a built-in-self-test (BIST) to be executed to test the cache memory, the BIST being operable to determine whether any of the subdivisions is defective. When it is determined that one of the subdivisions of the cache memory determined defective by the BIST is non-repairable, the SE logically deletes the defective subdivision from the system configuration, and the SE is operable to permit the processor to operate without the logically deleted subdivision. The SE is further operable to determine that the processor is defective when a number of the defective subdivisions exceeds a threshold.
REFERENCES:
patent: 4523313 (1985-06-01), Nibby, Jr. et al.
patent: 4992984 (1991-02-01), Busch et al.
patent: 5070502 (1991-12-01), Supnik
patent: 5659551 (1997-08-01), Huott et al.
patent: 5805789 (1998-09-01), Huott et al.
patent: 5835502 (1998-11-01), Aipperspach et al.
patent: 5835504 (1998-11-01), Balkin et al.
patent: 5953745 (1999-09-01), Lattimore et al.
patent: 5958068 (1999-09-01), Arimilli et al.
patent: 6006311 (1999-12-01), Arimilli et al.
patent: 6125465 (2000-09-01), McNamara et al.
patent: 6173357 (2001-01-01), Ju
patent: 6222211 (2001-04-01), Chen
patent: 6351789 (2002-02-01), Green
patent: 6671644 (2003-12-01), Huismann et al.
patent: 6671822 (2003-12-01), Asher et al.
patent: 6675319 (2004-01-01), Chen
patent: 6720652 (2004-04-01), Akram et al.
patent: 6918071 (2005-07-01), Cherabuddi et al.
patent: 6954827 (2005-10-01), Park et al.
patent: 2003/0088811 (2003-05-01), Cherabuddi et al.
patent: 2004/0088603 (2004-05-01), Asher et al.
patent: 0632380 (1995-01-01), None
patent: 1014797 (1989-01-01), None
T. Jaber et al. “Using Partially Good Data Cache VLSI Chips in an Environment of Flexible System Configuration,” IBM Technical Disclosure Bulletin, vol. 32, No. 12, May 1990, pp. 139-141.
K. Massoudian et al. “Dynamic Remapping of Bad Memory Segments During Power-On Self-Test in a PS/2 System” IBM Technical Disclosure Bulletin, vol. 33, No. 11, Apr. 1991, p. 217.
Huott William V.
Lund David J.
Marz Kenneth H.
Mechtly Bryan L.
Patel Pradip
Augspurger Lynn L.
International Business Machines - Corporation
McCarthy Christopher
LandOfFree
Self test method and apparatus for identifying partially... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Self test method and apparatus for identifying partially..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Self test method and apparatus for identifying partially... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3922007