Self test for the phase angle of the data read clock signal DQS

Details Self test for the phase angle of the data read clock signal DQS Self test for the phase angle of the data read clock signal DQS

2007-12-11

2007-12-11

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Read/write circuit

Including signal comparison

C365S233100, C365S201000

Reexamination Certificate

active

11227714

ABSTRACT:
The invention relates to a semiconductor memory apparatus having at least one clock input contact for inputting an external clock signal, at least one clock output contact for outputting a data read clock signal for reading data stored in the semiconductor memory apparatus, at least one data contact for outputting data stored in the semiconductor memory apparatus, at least one phase adjustment device which is designed for approximately adjusting a phase of the data read clock signal on the basis of a phase of the external clock signal at least one phase difference test device which is designed for approximately detecting a phase difference between the phase of the data read clock signal and the phase of the external clock signal and for outputting a test result on the basis of the detected phase difference.

REFERENCES:
patent: 6069508 (2000-05-01), Takai
patent: 6667913 (2003-12-01), Okuda et al.
patent: 198 25 986 (1998-12-01), None

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