Static information storage and retrieval – Read/write circuit – Testing
Patent
1995-01-20
1996-11-12
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Testing
371 214, G11C 2900
Patent
active
055746900
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
1. Prior Art
The present invention relate to a self-test device for memory arrangements, decoders or the like for use during on-line operation, means for checking a plurality of word lines being provided.
2. Background Information
IEEE Trans. on Computer-Aided Design, Vol. 9, No. 6, June 1990, pp. 567-572, "A Realistic Fault Model and Test Algorithms for Static Random Access Memories," discusses techniques for off-line testing of memory arrangements which are known. These techniques can also be used to some extent as a "built-in self-test"; however, due to the numerous required test patterns and the destruction of the memory content, they can be used only conditionally for testing during routine operation ("quasi on-line"). Furthermore, the required test length prohibits their use in the on-line test.
In addition, "Defect and Fault Tolerance in VLSI Systems," in Koren, Plenum Press, New York, 1989 (Design of Fault-Tolerant DRAM with new on Chip ECC--Mazumber, P.), discusses arrangements having coding of data which are known in which different codes are used. However, a coding of this sort prevents only a very small share of the possible hardware errors in the memory arrangement to be checked.
Finally, there are techniques in which the actual selected memory cell is determined via a ROM and its address is compared with the desired address.
In particular, row and column addresses are read out and compared with the input address in a self-checking checker. Techniques of this sort are known, for example, from "Self-checking Flash-EPROM," M. Nicolaidis, contribution to the JESSI SE 11 project, presentation in the lecture on Sep. 16, 1992 in Grenoble (France), or from "Efficient ubist implementation for microprocessor sequencing parts," M. Nicolaidis, June 1990, publication of the Institute IMAG/TIM 3, 46 Avenue Felix Viallet, 38031 Grenoble (France). However, these self-test devices are very expensive in terms of circuit technology and cover on their own only the decoder errors.
Overall, the known self-test devices and techniques either respectively cover on their own only very few possible errors, or are very expensive with regard to the necessary hardware, or are very time-consuming such that they are not suitable for on-line operation.
SUMMARY OF THE INVENTION
The self-test device according to the present invention has, in contrast, the advantage that, for monitoring the word lines, only a 1-out-of-n checker is used which, during on-line operation, delivers an error message via an error detector if more than one word line is active simultaneously. As a result, most error sources in the decoder are detected, and this self-test can be performed at a very low cost and at high speed. Practically all addressing errors can be detected, provided that it is ensured, through the coding of the address with a suitable code in conjunction with constructive design features (miles) and a code check, that a single error does not influence two word lines in the opposite direction. Also, it can be ensured through the choice of the data code that a faulty code is detected if no word line is activated.
In one preferred refinement of the 1-out-of-n checker according to the present invention, each word line in the check matrix is connected respectively to gate terminals (control connections) of z switches of a switching matrix by way of which z test lines, having a first potential (Vdd) applied to them, can be connected either to terminals (connections) at a second potential (Vss) or to a sensor line, which also has the first potential (Vdd) applied to it corresponding to the coding of the re respective word line, the error detector being connected to the sensor line and designed as a current or voltage sensor. If two word lines are simultaneously active, the error detector is connected to the second potential via two switches such that an increased current or rather a change in the potential, can be sensed.
The switches of the switching matrix are expediently designed as FET transistors, and the termi
REFERENCES:
patent: 3712537 (1973-01-01), Carita
Heinz Peter Holzapfel, "Fehlertolerante VLSI-Prozessoren", Lehrstuhl fur Integrierte Schaltungen der Technischen Universitat Munchen, Jun. 24, 1986, pp. 50-73.
P. Mazumder, "Design of a Fault-Tolerant Dram With New On-Chip ECC", Defect and Fault Tolerance in VLSI Systems, vol. 1, p. 85-92.
John Wakerly, "Error Detecting Codes, Self-Checking Circuits and Applications", Computer Design and Architecture Series, vol. 1, pp. 85-92.
M. Nicolaidis, "Efficient Ubist Implementation for Microprocessor Sequencing Parts", Reliable Integrated Systems Group, IMAG/TIM3, 46 avenue Felix Viallet, 38031 Grenoble Cedex, France, pp. 7-8.
R. Dekker et al., "A Realistic Fault Model and Test Algorithms for Static Random Access Memories", IEEE Transactions on Computer-Aided Design, vol. 9, No. 6, Jun. 1990, pp. 567-572.
Boehl Eberhard
Kesel Frank
Popek Joseph A.
Robert & Bosch GmbH
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