Self-test circuit and method utilizing interlaced scanning for t

Details Self-test circuit and method utilizing interlaced scanning for t Self-test circuit and method utilizing interlaced scanning for t

1996-12-05

1999-06-29

Tu, Trinh L.

Excavating

371 2231, 365201, 36518904, 36518905, 36518912, G11C 2900, G01R 3128

Patent

active

059178329

ABSTRACT:
A self-test circuit and method for efficiently testing a semiconductor memory device are described. A plurality of memory cells is provided with each memory cell comprising a storage location with a data value stored therein. A control circuit is provided for controlling a test of the memory cells. A shift multiplexer is provided for generating a write signal responsive to a shift signal received over a connection to the control circuit. A latch multiplexer is provided for generating a read signal responsive to a latch signal received over a connection to the control circuit. A plurality of output registers are provided with each output register connected to the latch multiplexer and including a connection for reading the data value from the storage location of one of the memory cells responsive to the latch multiplexer and a further connection for generating the data value as an output. A plurality of input registers are provided with each input register connected to the shift multiplexer and including a connection for receiving the data value as an input and a connection for writing the data value into the storage location of one of the memory cells responsive to the shift multiplexer. A plurality of multiplexers are provided with each multiplexer being operatively interconnected between one of the output registers to receive the output data value generated therefrom and one of the input registers to generate the input data value received thereinto. The control circuit is interconnected between a leftmost output register and a rightmost multiplexer to receive the data value generated from the leftmost output register and to generate a test input signal as the input data value into the rightmost multiplexer.

REFERENCES:
patent: 4493077 (1985-01-01), Agrawal et al.
patent: 4953128 (1990-08-01), Kawai et al.
patent: 5504756 (1996-04-01), Kim et al.
patent: 5519714 (1996-05-01), Nakamura et al.
patent: 5715255 (1998-02-01), Whetsel

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