Self-test circuit and memory device incorporating it

Details Self-test circuit and memory device incorporating it Self-test circuit and memory device incorporating it

2005-06-14

2005-06-14

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

Reexamination Certificate

active

06907555

ABSTRACT:
The present invention is a self-test circuit (BIST) incorporated in the memory device, which is activated in response to a test activation signal from outside. When this self-test circuit is activated in response to a test activation signal (WBIZ) from outside, it generates a test operation command (WBI-CMD), generates a test address (WBI-ADD), and generates test data (WBI-DATA). Furthermore, after the self-test circuit writes the test data to a memory cell, it effects a comparison to establish whether or not the read data that is read from this memory cell is the same as the test data that was written thereto and stores information as to the result of this comparison. This comparison result information is then output to the outside.

REFERENCES:
patent: 6108252 (2000-08-01), Park
patent: 61-54550 (1986-03-01), None
patent: 11-39226 (1999-02-01), None

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