Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
1998-12-16
2001-08-14
Tu, Christine T. (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S763000, C714S766000, C714S800000
Reexamination Certificate
active
06275960
ABSTRACT:
FIELD OF APPLICATION
The present invention relates to memories, and, more particularly, to flash EPROM memories or more simply to flash memories erasable and reprogrammable by sectors.
BACKGROUND OF THE INVENTION
There is a continuing evolution towards flash memory devices with higher and higher memory capacities, reached by reducing the size of memory cells. As known to those skilled in the art, the limitations in scaling down integrated devices, besides being due to technological limitations of the fabrication processes, may also be determined by criticalities that negatively affect reliability of the produced devices and therefore reduce the yield of the fabrication process.
Usually, fabricated devices are tested in relation to known critical mechanisms which are accentuated by the scaling down process. This is done by subjecting the devices to specially designed testing cycles. During these testing cycles one of the factors for enhancing critical aspects is the temperature. Increased temperature generally tends to worsen or accelerate the failure mechanisms of those devices that contain elements or cells operating at the limit of their reliability.
It has been recently discovered a new failure mechanism of flash memories which apparently is induced exclusively by cyclings, that is, by the number of erasing and programming cycles to which the memory device is subjected. The new failure manifests itself as a loss of charge of single cells during prolonged tests of data retention of data programmed at a low temperature (for example, at ambient temperature).
Although the probability of this phenomenon, in terms of number of lost bits is very low (ranging from 10
−8
to 10
−9
), its occurrence implies the failure of memories commonly having a capacity of many megabytes. This results in missing the specified failure targets required by many applications for these devices.
On the other hand, this type of failure hardly lends itself to a preventive screening at the level of the testing process because the failure mechanism is induced by the number of cycles and the loss of charge may not otherwise be accelerated. This problem has been recently approached at a system level by introducing a dedicated refresh operation of the contents of the programmed memory. However, this does not eliminate the problem, because it requires that the system be permanently powered. A peculiar characteristic of nonvolatile memories should be their capacity of retaining the programmed information, even in absence of power supply.
SUMMARY OF THE INVENTION
In view of the foregoing background an approach has now been found that uses a process of self-test and correction of loss of charge errors that may be performed at every power-on and/or pursuant to a command. The effectiveness rests on the fact that the number of bits that may cause this kind of failure through a loss of charge is relatively low and sufficiently so to statistically exclude the occurrence of two or more failures in a same sector of a multi-sector flash memory matrix.
REFERENCES:
patent: 4768193 (1988-08-01), Takemae
patent: 4939694 (1990-07-01), Eaton et al.
patent: 5151906 (1992-09-01), Sawada
patent: 5475693 (1995-12-01), Christopherson et al.
patent: 5581567 (1996-12-01), Chen et al.
patent: 5671239 (1997-09-01), Higashitani et al.
Cappelletti Paolo
Maurelli Alfonso
Olivo Marco
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Galanthay Theodore E.
STMicroelectronics S.r.l.
Tu Christine T.
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