Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate
2003-05-30
2004-11-16
Chang, Daniel D. (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
C714S744000
Reexamination Certificate
active
06819140
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a self-synchronous logic circuit having a test function and to a method of testing a self-synchronous logic circuit. More specifically, the present invention relates to a self-synchronous logic circuit having a function of testing a logic circuit having a self-synchronous pipeline and to a method of testing a self-synchronous logic circuit.
2. Description of the Background Art
Generally, a logic circuit in an LSI (Large Scale Integration) forms a pipeline in which a plurality of stages are connected in series, with state storing elements such as flip-flops serving as boundaries. Data processing in the pipeline proceeds such that the data to be processed is input to a head stage of the serial connection (hereinafter simply referred to as the head stage), processing is done in each stage, and eventually, a result of processing is output from the last stage. In a synchronous circuitry, all the stages of the pipeline operate in synchronization with a common clock. Logic circuits, however, come to have ever increasing scale, higher speed of operation, and smaller design rule, and therefore, it becomes more and more difficult to attain clock distribution with adjusted delays that is necessary in physical design of synchronous circuits over an entire chip or an entire module. Accordingly, LSI logic circuits such as a data driven processor having a self-synchronous pipeline have been proposed, in which clock distribution is performed only within the stages of the pipeline, and clocks are transferred by handshake between the stages of the pipeline so as to eliminate the necessity of a common clock to attain synchronization. Each stage of the pipeline of the data driven processor includes a self synchronous signal control circuit handling clock transfer, and a circuit for data processing. In the entire pipeline, the former is in charge of clock transfer, and the latter provides a data path. (In the following description, the stage of interest will be sometimes referred to as the present stage, the stage preceding the stage of interest will be simply referred to as the preceding stage, and the stage succeeding the stage of interest will be simply referred to as the succeeding stage. Further, the n-th stage from the head stage will be simply referred to as the n-th stage.)
FIG. 8
shows a characteristic portion of a conventional logic circuit having a self-synchronous pipeline. Referring to
FIG. 8
, pipeline stage registers (hereinafter simply referred to as registers)
804
,
805
and
806
each constitute a stage of the pipeline successively transferring a data path input from a preceding stage to a succeeding stage. Between an output of register
804
and an input of register
805
, a combination circuit
107
is connected, and between an output of register
805
and an input of register
806
, a combination circuit
108
is connected. Combination circuits
107
and
108
process data output from registers
804
and
805
of the preceding stages, respectively, and are formed simply by a combination of basic gate circuits, without any circuit such as a flip-flop for holding an internal state.
Corresponding to registers
804
,
805
and
806
, self-synchronous signal control circuits
801
,
802
and
803
are provided, respectively. Self-synchronous signal control circuits
801
,
802
and
803
handshake with each other while outputting, from a terminal CP, clock pulses to the corresponding registers. Upon reception of the clock pulses from the corresponding self-synchronous signal control circuits, registers
804
,
805
and
806
take data from the preceding stage, hold the same and output to the succeeding stage.
FIG. 9
is a specific block diagram of the self-synchronous signal control circuit shown in FIG.
8
. Referring to
FIG. 9
, a request signal CI representing, by two states of the signal, transfer request and transfer complete is input from the preceding stage to a CI input terminal
201
. An RO output terminal
202
returns to the preceding stage an acknowledge signal RO that represents, by two states of the signal, transfer permission permitting output of the transfer request of the request signal CI from the preceding stage, and transfer reception indicating reception of the transfer request. In accordance with the request signal CI of the preceding stage indicating transfer complete and the acknowledge signal RI from the succeeding stage indicating transfer permission, a CP output terminal
205
issues a clock pulse for storing data in the register. A CO output terminal
203
applies, through a delay element
210
to the succeeding stage, a request signal representing, by two states of the signal, transfer request and transfer complete. An RI input terminal
204
receives, from the succeeding stage, an acknowledge signal RI representing, by two states of the signal, transfer permission permitting output of the transfer request from the CO output terminal
203
to the succeeding stage, and transfer reception indicating reception of the transfer request by the succeeding stage.
Further, the self-synchronous signal control circuit includes a flip-flop
901
, a 4-input NAND gate
209
and a flip-flop
208
. Flip-flop
901
holds a transfer request receiving state, flip-flop
208
holds a transfer request issuing state for the succeeding stage, and NAND gate
209
attains synchronization among flip-flops
901
,
208
, the CI input and the RI input. The request signal CI is input to an S input terminal of flip-flop
901
, and the request signal CI is also applied to one input terminal of NAND gate
209
. A Q output signal of flip-flop
901
is applied to one input terminal of NAND gate
209
, and a Q-inverted output (/Q) of flip-flop
901
is output to an RO output terminal
202
. The RI signal that has been input to RI input terminal
204
is applied to one input of NAND gate
209
and a reset input terminal of flip-flop
208
. An output signal of NAND gate
209
is applied to a reset input terminal of flip-flop
901
and to a set input terminal of flip-flop
208
. The Q output of flip-flop
208
is output to a CP output terminal
205
, and the Q-inverted output (/Q) is applied to a CO output terminal
203
and to NAND gate
209
.
An MRB input terminal
206
supplies a reset signal MRB for setting flip-flops
901
and
208
to the initial state.
FIGS. 10A
to
10
L are timing charts illustrating the operation related to
FIGS. 8 and 9
. The timing charts represent changes of signals related to self-synchronous signal control circuit
801
at CI input terminal
801
CI, CO output terminal
801
CO, RI input terminal
801
RI, RO output terminal
801
RO, and CP output terminal
801
CP. Similarly, changes of signals related to self-synchronous signal control circuit
802
at CI input terminal
802
CI, CO output terminal
802
CO, RI input terminal
802
RI, RO output terminal
802
RO and CP output terminal
802
CP are represented, and changes of signals related to self-synchronous signal control circuit
803
at CI input terminal
803
CI, CO output terminal
803
CO, RI input terminal
803
RI, RO output terminal
803
RO and CP output terminal
803
CP are represented.
FIGS. 10A
to
10
L represent an operation when transfer request/complete is input once, with the stages of the pipeline being empty. Timings T
1
to T
4
are indicated in
FIGS. 10B and 10C
to facilitate understanding of the operation. The operation will be described with reference to
FIGS. 8
,
9
and
10
A to
10
L.
First, flip-flops
901
holding transfer request receiving state and flip-flops
208
holding the transfer request issuing state of the self-synchronous signal control circuits of all the stages are reset by a pulse input of the reset signal MRB shown in FIG.
10
A. At this time, RO output terminals are at the transfer permission state of H, and the CO outputs are at the transfer complete state of H in all self-synchronous signal control circuits.
To the CI input terminal
801
CI of self-synchronous signal control
Horiyama Takashi
Yamanaka Hidekazu
Chang Daniel D.
Sharp Kabushiki Kaisha
LandOfFree
Self-synchronous logic circuit having test function and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Self-synchronous logic circuit having test function and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Self-synchronous logic circuit having test function and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3296080