Self-synchronous FIFO memory device having high access...

Details Self-synchronous FIFO memory device having high access... Self-synchronous FIFO memory device having high access...

2005-09-06

2005-09-06

Thai, Tuan V. (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S100000, C711S154000, C711S169000, C710S057000, C710S058000, C710S061000

Reexamination Certificate

active

06941434

ABSTRACT:
An arbitration circuit adjusts timings of a write request signal from a first external device and a read request signal from a second external device. An RAM performs data write/data read in response to the external write request/read request. A next-state function is provided, which has a function to calculate a write address/read address to be input to the RAM in response to the external write request/read request, and a function to accurately count data stored in a FIFO.

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