Self-synchronizing bit error analyzer and circuit

Details Self-synchronizing bit error analyzer and circuit Self-synchronizing bit error analyzer and circuit

2008-05-21

2010-02-09

Trimmings, John P (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error count or rate

C714S715000, C714S043000, C714S056000, C714S704000, C714S709000, C714S716000, C714S717000, C714S724000, C714S728000, C714S731000, C714S732000, C714S734000, C714S739000, C714S744000, C714S748000, C714S712000

Reexamination Certificate

active

07661039

ABSTRACT:
A self-synchronizing data bus analyzer is provided which can include a generator linear feedback shift register (LFSR) to generate a first data set, and can include a receiver LFSR to generate a second data set. The data bus analyzer may also include a bit sampler to sample the first data set received through a data bus coupled to the generator LFSR and output a sampled first data set. A comparator can be included to compare the sampled first data set with the second data set generated by the receiver LFSR and provide a signal to the receiver LFSR to adjust a phase of the receiver LFSR until the second data set is substantially the same as the first data set.

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