Self-synchronising bit error analyser and circuit

Details Self-synchronising bit error analyser and circuit Self-synchronising bit error analyser and circuit

2008-07-22

2008-07-22

Trimmings, John P (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Transmission facility testing

C714S043000, C714S056000, C714S704000, C714S707000, C714S709000, C714S716000, C714S717000, C714S724000, C714S728000, C714S731000, C714S732000, C714S734000, C714S739000, C714S744000, C714S798000, C714S712000

Reexamination Certificate

active

07404115

ABSTRACT:
A self-synchronising data bus analyser comprising a generator LFSR, a receiver LFSR and a comparatorwherein the generator LFSR generates a first data set which is transmitted through a data bus to the comparator; andwherein the comparator compares the first data set with a second data set generated by the receiver LFSR and adjusts the receiver LFSR until the second data set is substantially the same as the first data set.

REFERENCES:
patent: 4667327 (1987-05-01), Bright et al.
patent: 4747105 (1988-05-01), Wilson et al.
patent: 4754457 (1988-06-01), Bright et al.
patent: 5228042 (1993-07-01), Gauthier et al.
patent: 6560727 (2003-05-01), Pierson et al.
patent: 6636994 (2003-10-01), Waschura et al.

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