Self-sweeping autolock PLL

Details Self-sweeping autolock PLL Self-sweeping autolock PLL

1998-07-10

2004-03-09

Corrielus, Jean B. (Department: 2634)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C327S156000

Reexamination Certificate

active

06704382

ABSTRACT:

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
N/A
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a phase-locked loop (“PLL”) circuit. In particular, the present invention relates to a phase-locked loop circuit with a digital phase detector and a self-sweeping autolock sub-circuit.
2. Description of the Related Art
The increasing use of digital communications has brought with it the need for innovative solutions to new communications challenges resulting from the nature of digital communications. A need also exists for improved solutions for general communications challenges that may have been solved adequately for legacy analog communications systems, but that now require enhanced solutions for digital communications.
One such problem particular to digital communications is the need to extract a digital clock from a data stream. Though the expected data rate of the data stream may be known, the actual data rate and signal quality received may vary significantly. Factors that affect the frequency and quality of the data stream include imperfections in the transmitting and receiving equipment, an increasingly hostile air interface, the complications arising from the increasing use of mobile transmitters and receivers, and the like.
In the past, the phase-locked loop (“PLL”) has been proposed to extract clock signals from data streams. However, conventional PLLs have experienced some limitations. One limitation related to PLLs in general is that it is difficult to lock to the phase of an input signal having a frequency out of a range of frequencies onto which a particular PLL is designed to lock. A popular solution to this problem is to add a frequency sweep circuit which forces the output frequency of the PLL to sweep across a frequency range in an attempt to direct the output PLL frequency to pass close enough to the frequency of the input waveform to enable the PLL to phase-lock. Most conventional implementations of this strategy require that the frequency sweep circuitry use a separate oscillator and corresponding phase-lock detection circuitry. However, one disadvantage of the conventional frequency sweep circuit is that it requires more complex circuitry and a higher resulting cost, larger size and less reliability. Other implementations of the PLL output frequency sweeping strategy involve the utilization of positive feedback in the PLL active loop filter as disclosed in U.S. Pat. No. 4,206,420. The system of the '420 patent attempts to eliminate the need for a separate sweep oscillator and phase-lock detection circuitry. However, the system of the '420 patent has a disadvantage in that it causes the response characteristics of the loop filter to be dependent upon whether the PLL is in a phase-lock mode or a phase-lock-acquisition mode. In addition, the loop filter response characteristics of the '420 patent are affected in such a way that a steady state phase error is introduced when the PLL is in the phase-lock mode.
Another limitation of conventional PLLs for extracting frequency components of an input digital data stream relates to the phase detectors employed in such PLLs. The phase detector used in the typical PLL is a multiplying type of detector. Multiplying phase detectors function well in the presence of noise. However, a disadvantage is that multiplying phase detectors have a limited frequency range over which they may achieve phase-lock, thereby resulting in the need for an additional sweep generator. Another solution occasionally employed is the use of a phase frequency detector which, when out of lock, will steer the PLL back in the direction necessary to achieve lock. A disadvantage of the conventional phase frequency detector is that a noisy data stream may contain extra pulses which may cause the phase frequency detector to identify an “out of lock” state when the PLL in fact is still phase locked. A false “out of lock” identification causes the PLL to lose lock temporarily in an attempt to correct itself. The unnecessary corrective action can result in a missing cycle in the PLL output clock which may then result in missing data bits, which is less than desirable.
Therefore, a need remains for an improved PLL that is able to overcome the foregoing problems.
SUMMARY OF THE INVENTION
It is an object of the present invention to address the aforementioned problems through the implementation of an improved phase-lock loop design with a digital phase detector and self-sweeping autolock sub-circuit.
One object of the present invention is to provide a phase-lock loop with the ability to lock directly to a binary data stream.
Another object of the present invention is to provide a phase-lock without a separate sweep oscillator and the related phase-lock detection circuitry.
Another object of the present invention is to provide a phase-lock loop which introduces an insignificant steady-state phase error.
Another object of the present invention is to provide a phase-lock loop which automatically enters the sweeping mode of operation in the absence of phase-lock and which automatically leaves the sweeping mode when phase-lock is acquired.
Another object of the present invention is to provide a phase-lock loop with the ability to accept noisy data streams without losing phase-lock.
Another object of the present invention is to provide a sweep control circuit integrated into the phase-lock loop circuit in a manner such that it does not affect the response characteristics of the loop filter.
These and other objectives are achieved by an improved phase-lock loop circuit comprising a phase detector, a loop filter, and a voltage controlled oscillator. The phase detector samples the phase-lock loop input signal at various points in a cycle of the phase-lock loop output signal and outputs a signal representative of the point of the phase-lock loop output cycle at which a logic state transition of the input signal is detected. In addition, a self-sweeping autolock circuit interacts with the loop filter in such a manner that the self-sweeping autolock circuit commands the loop filter to sweep its output signal when phase-lock is absent and the loop filter halts the sweep of its output signal when phase-lock is acquired.


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