Adhesive bonding and miscellaneous chemical manufacture – Differential fluid etching apparatus – For liquid etchant
Reexamination Certificate
2002-01-18
2003-06-03
Utech, Benjamin L. (Department: 1763)
Adhesive bonding and miscellaneous chemical manufacture
Differential fluid etching apparatus
For liquid etchant
Reexamination Certificate
active
06572731
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method and apparatus for polishing surfaces that have special requirements or that impose unique challenges of surface polishing.
(2) Description of the Prior Art
Chemical Mechanical Polishing is a method of polishing the surface of a layer of semiconductor material, such as the surface of a semiconductor substrate, to a high degree of planarity and uniformity. The process is used to planarize semiconductor surfaces prior to the fabrication of semiconductor circuitry therein and thereon, and is also used to remove features of high elevation that are created during the fabrication of the microelectronic circuitry on the substrate. One typical chemical mechanical polishing process uses a large polishing pad, that is located on a rotating platen against which a substrate is positioned for polishing, and a positioning member which positions and biases the substrate on the rotating polishing pad. Chemical slurry, which may include abrasive materials, is maintained on the polishing pad to modify the polishing characteristics of the polishing pad in order to enhance the polishing of the substrate.
The use of chemical mechanical polishing to planarize semiconductor substrates continues to pose challenges, particularly where the process is used to evenly and uniformly remove high elevation features across the surface of a substrate. One primary problem, which has limited the used of chemical mechanical polishing in the semiconductor industry, is the limited ability to predict, much less control, the rate and uniformity at which the process will remove material from the substrate. As a result, CMP remains a labor-intensive process because the thickness and uniformity of the substrate must be constantly monitored to prevent over-polishing or inconsistent polishing of the surface of the substrate.
The profile of the polishing pad plays an important role in determining good overall polishing results. The polishing pad can, for instance, be profiled thick at the inner diameter of the polishing pad as compared to the outer diameter of the polishing pad and visa versa. The profile of the polishing pad is typically achieved by trial and error and by adjusting the position of a diamond dresser. The function of the diamond dresser is to maintain and/or restore the polishing characteristics of the polishing pad to the maximum extent possible during the polishing operation and in doing so to extend the useful life or the operating characteristics of the polishing pad. This method of profiling the polishing pad is destructive, time consuming and causes the loss of the polishing pad. Since this measure of the polishing pad profile can only be performed at the end of the useful life of the polishing pad, the wrong profile can only be detected after the polishing pad has served its useful life.
The polishing process is carried out until the surface of the wafer is ground to a highly planar state. During the polishing process, both the wafer surface and the polishing pad become abraded. After numerous wafers have been polished, the polishing pad becomes worn to the point where the efficiency of the polishing process is diminished and the rate of removal of material from the wafer surface is significantly reduced. It is usually at this point that the polishing pad is treated and restored to its initial state so that a high rate of uniform polishing can once again be obtained.
The invention addresses these and other concerns in providing a method and apparatus that specifically results in improved uniformity and planarity of the surface of the substrate and of the individual die that are being polished.
U.S. Pat. No. 5,709,593 (Guthrie et al.) shows a slurry distribution system.
U.S. Pat. No. 6,235,635 B1 (Roy) shows a CMP tool with in-situ open loop slurry distribution.
U.S. Pat. No. 6,234,868 BI (Easter et al.) shows a chemical-mechanical polish (CMP) slurry distribution system.
U.S. Pat. No. 5,775,983 (Shendon et al.) shows a method to condition a CMP pad.
U.S. Pat. No. 5,688,360 (Jairath) and U.S. Pat. No. 6,231,427 B1 (Talieh et al.) are related CMP and slurry distribution patents.
SUMMARY OF THE INVENTION
A principle objective of the invention is to provide a method and apparatus of Chemical Mechanical Polishing that assures even distribution of slurry over the surface that is being polished.
Another objective of the invention is to provide a method and apparatus of Chemical Mechanical Polishing that significantly reduces usage of required slurry, thus significantly reducing cost of polishing a semiconductor surface.
Yet another objective of the invention is to provide a method and apparatus of Chemical Mechanical Polishing that results in improved surface planarity and improved surface uniformity after the process of polishing has been completed.
A still further objective of the invention is to provide a method and apparatus of Chemical Mechanical Polishing that allows for uniform removal of spent slurry from the surface that is being polished.
In accordance with the objectives of the invention a new method is provided for the polishing of semiconductor surfaces such as the surface of a substrate, the surface of deposited copper and the surface of layers of low-k dielectric. The polishing method and apparatus of the invention comprise a new slurry delivery design whereby at least two different slurries can be independently controlled and mixed for delivery to a slurry container. The slurry container is in direct physical contact with a polishing pad, providing for the mixed slurry to be distributed over the surface of the polishing pad.
REFERENCES:
patent: 5688360 (1997-11-01), Jairath
patent: 5709593 (1998-01-01), Guthrie et al.
patent: 5775983 (1998-07-01), Shendon et al.
patent: 6156659 (2000-12-01), Roy
patent: 6231427 (2001-05-01), Talieh et al.
patent: 6234868 (2001-05-01), Easter et al.
patent: 6235635 (2001-05-01), Roy
patent: 6348124 (2002-02-01), Garbett et al.
Chartered Semiconductor Manufacturing Ltd.
MacArthur Sylvia R.
Pike Rosemary L. S.
Saile George O.
Utech Benjamin L.
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