Self reverse bias low-power high-performance storage...

Details Self reverse bias low-power high-performance storage... Self reverse bias low-power high-performance storage...

2006-01-31

2006-01-31

Phan, Trong (Department: 2827)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S156000, C365S203000

Reexamination Certificate

active

06992915

ABSTRACT:
An integrated circuit is provided comprising a first NMOS transistor; a first PMOS transistor; a second NMOS transistor; a second PMOS transistor; a first bias voltage node coupled to a first source/drain of the first NMOS transistor; a second bias voltage node coupled to a first source/drain of the second PMOS; a third bias voltage node coupled to a gate of the first PMOS transistor; a fourth bias voltage node coupled to a gate of the second NMOS transistor; a pull-up node coupling a second source/drain of the first NMOS transistor to a first source/drain of the first PMOS transistor; a pull-down node coupling a second source/drain of the second PMOS transistor to a first source/drain of the second NMOS transistor; an input node; a storage node coupling a second source/drain of the first PMOS transistor to a second source/drain of the second NMOS transistor; an output node; an input switch coupled to controllably communicate an input data value from the input node to a gate of the first NMOS transistor and to a gate of the second PMOS transistor; and an output switch coupled to controllably communicate a stored data value from the storage node to the output node.

REFERENCES:
patent: 5668770 (1997-09-01), Itoh et al.
patent: 58009290 (1983-01-01), None
International Search Report mailed Jun. 3, 2005, for PCT application No. PCT/US03/09599 filed on Mar. 27, 2003, 6 pages.

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