Self-restoring single event upset (SEU) hardened multiport...

Static information storage and retrieval – Systems using particular element – Flip-flop

Reexamination Certificate

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Details

C365S230050

Reexamination Certificate

active

06215694

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to integrated circuits in general, and in particular to mutiport memory cell circuits. Still more particularly, the present invention relates to a single event upset hardened mutiport memory cell.
2. Description of the Prior Art
Multiport memories are random access memories that have multiple ports to enable parallel accesses, such as simultaneously reading a first memory location via a first port and writing a second memory location via a second port. Typically, multiport memories find their applications within integrated circuit devices as register files. A register file is a temporary buffer for storing intermediate results (and arguments) that are produced and used by various functional parts of an integrated circuit device, as it is well-known to those skilled in the relevant art.
In certain environments, such as satellite orbital space, in which the level of radiation is relatively intense, integrated circuit devices that utilize static random access memories (SRAMs) as memory cells for a storage element, such as a register file, are more susceptible to single event upsets (SEUs) or soft errors. These SEUs are typically caused by electron-hole pairs created by, and travelling along the path of, a single energetic particle as it passes through the SRAM cells. Should the energetic particle generate a critical charge within a storage node of an SRAM cell, the logic state of the SRAM cell will be upset, and erroneous results may be generated.
SUMMARY OF THE INVENTION
In accordance with a preferred embodiment of the present invention, a single event upset hardened register file cell includes a storage cell, one or a pair of write bitlines, one or a pair of read bitlines. The storage cell, which is utilized for storing data, includes first and second sets of cross-coupled transistors and first and second sets of isolation transistors. The first and second sets of isolation transistors are respectively coupled to the first and second set of cross-coupled transistors such that two inversion paths are formed between the two sets of cross-coupled transistors and the two sets of isolation transistors. Coupled to the storage cell, the write bitline inputs write data to the storage cell. Also coupled to the storage cell, the read bitline outputs read data from the storage cell.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.


REFERENCES:
patent: 4873665 (1989-10-01), Jiang
patent: 5150326 (1992-09-01), Aoki
patent: 5157625 (1992-10-01), Barry
patent: 5189640 (1993-02-01), Huard
patent: 5311070 (1994-05-01), Dooley
patent: 5481495 (1996-01-01), Henkels

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