Self restoring logic

Electronic digital logic circuitry – Reliability – Redundant

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C326S009000, C326S011000, C326S013000, C326S014000

Reexamination Certificate

active

08081010

ABSTRACT:
Self Restoring Logic (SRL) provides for SEU tolerance in high speed circuits. An SRL cell is designed to be stable in one of two internal states. Upon an SEU event, the SRL cell will not transition between the internal stable states and recover from an SEU. SRL circuits are realized with SRL storage cells driving succeeding SRL storage cells directly or through combinational logic such that the corruption of any one internal state variable in the driving SRL cell and it's the associated combinational output logic can affect at most one internal state variable of the succeeding SRL cell. An SRL circuit does not allow propagation of single SEU faults.

REFERENCES:
patent: 4454589 (1984-06-01), Miller
patent: 4782467 (1988-11-01), Belt et al.
patent: 4783778 (1988-11-01), Finch et al.
patent: 4787057 (1988-11-01), Hammond
patent: 4797804 (1989-01-01), Rockett, Jr.
patent: 4852060 (1989-07-01), Rockett, Jr.
patent: 4888774 (1989-12-01), Kosuge et al.
patent: 5039876 (1991-08-01), Hochwald et al.
patent: 5111429 (1992-05-01), Whitaker
patent: 5157625 (1992-10-01), Barry
patent: 5278781 (1994-01-01), Aono et al.
patent: 5307142 (1994-04-01), Corbett et al.
patent: 5311070 (1994-05-01), Dooley
patent: 5374894 (1994-12-01), Fong
patent: 5398322 (1995-03-01), Marwood
patent: 5406513 (1995-04-01), Canaris et al.
patent: 5436572 (1995-07-01), Sugiyama
patent: 5436865 (1995-07-01), Kitazawa
patent: 5640341 (1997-06-01), Bessot et al.
patent: 5673407 (1997-09-01), Poland et al.
patent: 5867414 (1999-02-01), Kao
patent: 5870332 (1999-02-01), Lahey et al.
patent: 5875152 (1999-02-01), Liu et al.
patent: 5905290 (1999-05-01), Houston
patent: 5940318 (1999-08-01), Bessot
patent: 6005797 (1999-12-01), Porter et al.
patent: 6232794 (2001-05-01), Cox
patent: 6262597 (2001-07-01), Bauer et al.
patent: 6326809 (2001-12-01), Gambles et al.
patent: 6487134 (2002-11-01), Thoma et al.
patent: 6556045 (2003-04-01), Cohen
patent: 6573773 (2003-06-01), Maki et al.
patent: 6583470 (2003-06-01), Maki et al.
patent: 6597745 (2003-07-01), Dowling
patent: 6696873 (2004-02-01), Hazucha et al.
patent: 6725411 (2004-04-01), Gerlach et al.
patent: 6757122 (2004-06-01), Kuznetsov et al.
patent: 6791362 (2004-09-01), Carlson et al.
patent: 6826090 (2004-11-01), Chu et al.
patent: 6826778 (2004-11-01), Bopardikar et al.
patent: 6895547 (2005-05-01), Eleftheriou et al.
patent: 6928602 (2005-08-01), Yamagishi et al.
patent: 7023235 (2006-04-01), Hoff
patent: 7069492 (2006-06-01), Piret
patent: 7111221 (2006-09-01), Birru et al.
patent: 7127653 (2006-10-01), Gorshe
patent: 7162684 (2007-01-01), Hocevar
patent: 7482831 (2009-01-01), Chakraborty et al.
patent: 7489538 (2009-02-01), Maki
patent: 7958394 (2011-06-01), Bridgford
patent: 2006/0033523 (2006-02-01), Erstad et al.
patent: 2009/0189634 (2009-07-01), Rezgui et al.
patent: 2010/0026338 (2010-02-01), Fulcomer
Shuler R.L. et al. “Comparison of Dual-Rail and TMR Logic Cost Effectiveness and Suitability for FPGA's with Reconfigurable SEU Tolerance,” NSREC, Jul. 2008, 3pgs.
Shi, Quan et al., “New Design Techniques for SEU Immune Circuits,” NASA Symposium on VLSI Design, Nov. 2000, pp. 7.2.1-7.2.16.
Gambles, Jody W. et al., “Radiation Hardening by Design,” International Journal of Electronics, vol. 00, No. 00, Jan. 2006, pp. 1-20.
Massengill, L. et al., “Sub-100nm Radiation-Hardened IC Design” Single-Event Mechanisms Impacting Modeling and Simulation for Design, GOMAC Tech-07, Mar. 2007.
Massengill, L. et al., “Sub-100nm Radiation-Hardened IC Design” Single-Event Mechanisms Impacting Modeling and Simulation for Design, Proceedings of the Government Microcircuit Applications & Critical Technology Conference, Mar. 2007, pp. 309-313.
Whitaker, S. et al. “Ultra Low Power Electronics: Design Observations and CULPRiT Experiences,”Government Microcircuit Applications Critical Technology Conference, Mar. 2007, 4 pgs.
Gambles, Jody, “Radiation Hardness of Ultra Low Power CMOS Microcircuits,” Apr. 2003 igambles@cambr.uidaho.edu, Center for Advanced Microelectronic & Bimolecular Research, Univeristy of Idaho, 4 pgs.
Gambles, Jody W. et al.,“Radiation Effects and Hardening Techniques for Spacecraft System Microelectronics,” American Institute of Aeronautics and Astronautics, Inc., Jan. 2002, pp. 1-11.
Whitaker, Sterling et al., “Multiple Upset, Radiation Tolerant Combinational Logic Structure,” Proceedings of the 16thSingle Events Symposium, Apr. 2008, 6 pgs.
Radhakrishnan, Damu et al., “Formal Design Procedures for Pass Transistor Switching Circuits,” Apr. 1985 IEEE Journal of Solid-State Circuits, vol. SD-20, No. 2, pp. 531-536.
Hayduk, Robert J. et al., “Ultra-Low Powered Radiation-Tolerant CMOS VLSI,” 51stInternational Astronautical Conference, Oct. 2000, 12 pgs.
Haddad, Nadim et al. “The Path and Challenges to 90nm Radiation Hardened Technology,”Mar. 30, 2008, Hardened Electronics and Radiation Technology, pp. 269-273.
Baze, M.P. et al., “Angular Dependence of Single Event Sensitivity in Hardened Flip/Flop Designs,” IEEE Transactions on Nuclear Science, vol. 55, No. 6, Dec. 2008, pp. 3295-3301.
Calin, T. et al. “Upset Hardened Memory Design for Submicron CMOS Technology,” IEEE Transactions on Nuclear Science, vol. 43, No. 6, Dec, 1996, pp. 2874-2878.
Kang, S.M. et al., “CMOS Circuit Design for Prevention of Single Event Upset,” 1986 Proc. of 1986 International Conf. on Computer Design, Port Chester, NY, pp. 118158-118160.
Ma, T.P. et al., “Ionizing Radiation Effects in MOS Devices and Circuits,” Department of Electrical Engineering, Yale University, New Haven Connecticut and Sandia National Laboratories, Albuquerque, NM, a Wiley-Interscience Publication, John Wiley and Sons, Chapter 9, pp. 484-559.
Wiseman, D. et al. “Test Results for SEU and SEL Immune Memory circuits,” 5thNASA Symposium on VLSI Design 1993, NASA Space Engineering Research Center for VLSI System Design, University of New Mexico, 2650 Yale Suite #101, Albuquerque, New Mexico 87106, pp. 2.6.1-2.6.10.
Liu, M. Norley et al., “Low Power SEU Immune CMOS Memory Circuits,” IEEE Transaction on Nuclear Science, vol. 39, No. 6 Dec. 1992, NASA Space Engineering Research Center for VLSI System Design, University of Idaho, Moscow, Idaho 83843, pp. 1679-1681.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Self restoring logic does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Self restoring logic, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Self restoring logic will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4300724

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.