Self-resetting CMOS off-chip driver

Details Self-resetting CMOS off-chip driver Self-resetting CMOS off-chip driver

1994-10-11

1995-07-18

Westin, Edward P.

Electronic digital logic circuitry

Interface

Current driving

326 86, 326 17, 326 58, H03K 19094, H03K 1902

Patent

active

054345197

ABSTRACT:
A self-resetting CMOS off-chip diver includes a first pair of complementary FETs connected in series to receive first and second complementary drive signals from an on-chip source. A latch is connected to an output of the first pair of complementary FETs for latching said drive signals. The first pair of complementary FETs in combination with the latch form a unique "pulse catcher" circuit capable of catching and latching short duration pulses characteristic of the self-resetting (SR) mode, providing the transfer between the SR mode and the output static mode. A low power three state static driver circuit is comprised of first and second pass gates connected to pass an output of the latch and a second pair of complementary FETs respectively connected to receive outputs of the first and second pass gates to generate a static output for driving a transmission line. Pull-up and pull-down devices are connected to respective inputs of the second pair of complementary FETs and controlled by the control means to provide a three state function output. The three state static circuit provides high speed data transfer with a high drive capability full swing signal output. An enable circuit implementing four enable functions, including a testability function, is connected to the first and second pass gates to inhibit an output to the second pair of complementary FETs in the test mode. Pull-up and pull-down devices are connected to respective inputs of the second pair of complementary FETs and controlled by the enable circuit to provide the three state function output, including a high impedance state.

REFERENCES:
patent: 4806797 (1989-02-01), Yamazaki
patent: 4980580 (1990-12-01), Ghoshal
patent: 5023488 (1991-06-01), Gunning
patent: 5194764 (1993-03-01), Yano et al.
patent: 5315172 (1994-05-01), Reddy
patent: 5315187 (1994-05-01), Cheng
patent: 5346243 (1994-09-01), McClure
IBM Technical Disclosure Bulletin vol. 30, No. 2, Jul. 1987 by J. S. Mitby, et al, entitled "CMOS Driver Circuit", pp. 770-771.
IBM Technical discosure Bulletin vol. 31, No. 3, Aug. 1988 by T. Sunaga, entitled "Off-Chip Driver for Continuous Read Acess", pp. 318-320.
IBM Technical Disclosur Bulletin vol. 33, No. 7, Dec. 1990 by A. Correale, Jr., entitled "Circuit Scheme to Improve Chip Data Hold Time".

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