Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2002-05-01
2003-12-23
Phung, Anh (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C714S733000
Reexamination Certificate
active
06667918
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to memory arrays used in integrated circuit devices, and specifically to built-in mechanisms for replacing defective cells in such a memory array.
BACKGROUND OF THE INVENTION
The use of embedded memory arrays in Very Large Scale Integrated (VLSI) circuit devices is increasing. Such memory arrays enhance the ability of devices to support high-capacity and high-bandwidth applications. Memories, however, are typically subject to higher process defect-related failures than other elements of VLSI design, such as logic gates. Therefore, the use of embedded memory arrays typically makes devices more susceptible to failures due to manufacturing defects. As total memory on a device gets larger, the memory yield, and hence the device yield, may be dramatically reduced.
It is common practice to include redundant rows and columns in an embedded memory array. These redundant elements can be activated to repair defects inside the memory array. Typically, as part of the device manufacturing flow, the memories are tested, and defective bits in the arrays are detected. The memory array is then repaired by replacing the defective bits with rows or columns selected from the redundant rows and columns. The selection information (i.e., which rows/columns to use) is stored in a special non-volatile memory, typically implemented as a set of dedicated metal fuses, which are fabricated as part of the device. Programming the fuses requires a special step in the manufacturing process, wherein specialized and costly laser equipment is used to blow out selected fuses. Although fuse technology can help to increase device yield, the fuses themselves occupy a substantial area on the chip, therefore increasing device size. The additional manufacturing steps involved in blowing the selected fuses increase cost and can themselves reduce yield.
As an alternative to fuse technology, some VLSI devices with embedded memory arrays include Built-In Self-Test (BIST) circuits, which work together with on-chip repair logic to bypass faulty cells in the array. Such schemes are referred to generally as self-repair systems. As in fuse-based repair schemes, the memory array used for self-repair includes redundant rows and, in some cases, redundant columns. When the BIST circuit detects a fault at a given address in the array, it directs the repair logic to substitute one of the redundant array elements (typically either a cell or an entire row) for the faulty element. Thereafter, reads and writes addressed to the faulty array element are redirected by the repair logic to the redundant element that has been substituted for it.
A variety of self-repair schemes are described in the patent literature. For example, U.S. Pat. No. 5,764,878, whose disclosure is incorporated herein by reference, describes a built-in self-repair system for embedded memories, which is triggered automatically on power-up of the computer in which it is installed. The system includes a BIST circuit that tests for defective row memory lines or defective I/O memory blocks. (An I/O memory block is described as comprising at least one column memory line, but typically includes a plurality of column memory lines grouped together to form an I/O memory block.) When the address of a defective row line or I/O block is detected, it is dynamically repaired by a fault-latching and repair execution circuit, which reroutes the address locations of the defective row or block to new address locations associated with redundant rows or blocks.
The need to look up addresses of redundant rows that are used to substitute for defective rows can substantially increase the access time to the memory. U.S. Pat. No. 5,920,515, whose disclosure is incorporated herein by reference, describes a register-based redundancy circuit and method for built-in self-repair in a semiconductor memory device, which is aimed at solving this problem. The redundancy circuits are associated with failed row address stores to drive redundant row word lines, so that it is not necessary to supply and decode a substitute address in the normal way. The patent states that by providing redundancy handling at the predecode circuit level, rather than at a preliminary address substitution stage, access times to the memory array are improved.
As another example, U.S. Pat. No. 6,011,734, whose disclosure is incorporated herein by reference, describes a fuseless memory repair system, which uses a BIST circuit to determine a specific address at which a memory failure is detected. The address is stored in a latch. During normal operation, the address stored in the latch is compared to addresses being accessed in the memory. When a match occurs, a “HIT” signal is generated, which disables selection of the defective row in the memory array. A redundant row select signal selects the redundant row to replace the defective row.
U.S. Pat. No. 6,259,637, whose disclosure is also incorporated herein by reference, describes a method and apparatus for built-in self-repair of memory storage arrays. The memory array is produced with a number of redundant rows and redundant columns. A test circuit coupled to the memory array tests the memory cells in the rows of the array. In case of test failure, an error detection unit provides an error indication identifying the bit that failed. A control block keeps track of the errors, and decides whether to repair the failure with one of the redundant rows or the redundant columns.
U.S. Pat. No. 6,304,499, whose disclosure is likewise incorporated herein by reference, describes a semiconductor memory having redundant units of memory cells, along with a method of self-repair. A self-test unit carries out a functional test of the memory cells with a defined memory-retention time for the memory cell contents. The results of the test are analyzed to determine which of the normal memory units are to be replaced by redundant units. The memory units are programmed in accordance with the analysis result.
All the self-repair schemes described above require complex BIST circuits to identify the addresses of the faulty cells, along with address translation logic to redirect read and write data from faulty cells to the redundant cells that are substituted for them. Such BIST and addressing circuits occupy a substantial area on the chip, thus increasing the overall device cost and potentially reducing yield. Furthermore, as noted in the above-mentioned U.S. Pat. No. 5,920,515, the logic needed to identify reads and writes addressed to faulty cells and to look up the substitute redundant cell addresses reduces the access speed of the memory array. There is a need for a self-test and repair mechanism that overcomes these limitations of the prior art.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide improved methods and device architectures for self-repair of memory arrays.
It is a further object of some aspects of the present invention to provide built-in self-repair circuitry for an embedded memory array that requires a minimal amount of space on the chip on which it is fabricated.
It is yet a further object of some aspects of the present invention to provide built-in self-repair circuitry for a memory array that does not significantly affect the access time of the array.
In preferred embodiments of the present invention, an embedded memory unit comprises an array of memory lines (rows and columns), including a redundant memory line, preferably a redundant column. In other words, assuming the memory unit is designed to hold n lines of data, the array actually comprises n+1 lines of memory cells. Selection circuitry is coupled to the array so as to select n of the n+1 lines to which the data are to be written and from which the data are to be read.
To determine which lines to use, a Built-In Self-Test (BIST) circuit writes test data to the array and then reads the data from the array. The BIST circuit compares the data read from the array to the data written thereto, and generates a binary (pass/fail) o
Ben-Nun Boaz
Eliyahu Yuval
Leader Yuval
Shmueli Zvi
Zahavi Eitan
Mellanox Technologies Ltd.
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Phung Anh
LandOfFree
Self-repair of embedded memory arrays does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Self-repair of embedded memory arrays, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Self-repair of embedded memory arrays will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3154929