Self-refreshing of dynamic random access memory device and opera

Details Self-refreshing of dynamic random access memory device and opera Self-refreshing of dynamic random access memory device and opera

1989-04-14

1990-07-24

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Data refresh

365203, 36518909, G11C 800, G11C 1124

Patent

active

049439600

ABSTRACT:
There is disclosed a dynamic random access memory device of the type capable of periodic self-refresh cycles of operation. The DRAM includes the detector circuit for detecting the designation of the self-refresh mode and a voltage generator circuit for generating a voltage to precharge the bit line pair. During the self-controlled refresh cycle, the bit line pair is equalized and precharged to a voltage lower than Vcc/2. When it is attempted to set the time interval between the self-refresh cycles in order to reduce current consumption, the level of voltage stored in the memory cell capacitor tends to decrease due to charge leakage. However, it is implemented to provide and keep a potential difference between the precharge voltage on the bit line pair and the voltage stored in the capacitor thereby to secure the desired sensing margin for the sense amplifier.

REFERENCES:
patent: 4397003 (1983-08-01), Wilson et al.
patent: 4660180 (1987-04-01), Tanimura et al.
patent: 4688196 (1987-08-01), Inagaki et al.
patent: 4692689 (1987-09-01), Takemae
patent: 4716551 (1987-12-01), Inagaki
patent: 4736344 (1988-04-01), Yanagisawa
S. Saito "a 1Mb CMOS DRAM with Fast Page and Static Column Modes", IEEE International Solid-State Circuits Conference, Digest of Technical Papers, Feb. 15, 1985.
Michihiro Yamada et al., "A 64 Kbit MOS Synamic RAM with Auto/Self Refresh Functions", (The Journal of Electronics and Communications, Jan. 1983, vol. J66-C, No. 1, pp. 203-220).

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