Self-refreshing memory with on-chip timer test circuit

Details Self-refreshing memory with on-chip timer test circuit Self-refreshing memory with on-chip timer test circuit

1992-11-12

1994-06-14

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Data refresh

365201, G11C 1300

Patent

active

053216610

ABSTRACT:
A self-refreshing memory has a refresh timer that generates refresh requests at a certain rate, and a refresh address counter that generates refresh addresses by counting the refresh requests. A refresh test circuit receives test signals from automatic test equipment that cause it to disable the refresh timer, reset the refresh address counter, then enable the refresh timer for a certain interval. At the end of this interval the refresh test circuit disables the refresh timer again and generates an output signal such as a serial data signal indicating the current refresh address, or a pass-fail signal indicating whether the refresh address is equal to or greater than a preset pass value.

REFERENCES:
patent: 4672583 (1987-06-01), Nakaizumi
patent: 4682306 (1987-07-01), Sakurai et al.
patent: 4827476 (1989-05-01), Garcia
patent: 5119338 (1992-06-01), Saito
patent: 5157634 (1992-10-01), Dhong et al.

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