Self-refreshed capacitor memory cell

Details Self-refreshed capacitor memory cell Self-refreshed capacitor memory cell

1980-01-07

1981-09-29

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Data refresh

365189, G11C 1300

Patent

active

042926777

ABSTRACT:
This invention involves a capacitor memory cell (C.sub.S) of, typically the metal-oxide-semiconductor (MOS) capacitor type, which is accessed for reading and writing by means of an access network connected to the memory cell through a gating transistor (T.sub.1), and which is provided with an independent refresh network for maintaining the memory state of the cell in the absence of an access writing signal. The refresh network includes a pair of MOSFET (Metal Oxide Semiconductor Field-Effect Transistors) transistors (T.sub.2, T.sub.3) connected between the MOS capacitor and an A.C. refresh line which is independent of the electrical access network. Either a "full" or "empty" capacitor memory state, binary digital 1 or 0, respectively, is maintained without the need for interrupting the reading and writing of the MOS capacitor.

REFERENCES:
patent: 4203159 (1980-05-01), Wanlass

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