Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2000-02-07
2001-06-12
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S222000, C365S236000, C365S230060
Reexamination Certificate
active
06246619
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to dynamic random access memories (DRAM), and more particularly to means of reducing the manufacturing test time of DRAMs required to verify the self-refresh oscillator frequency through the use of logic functions.
2. Description of the Related Art
The present state of the art in verifying the self-refresh oscillator frequency requires the completion of a self-refresh operation for the entire DRAM. For a typical industry standard DRAM of 8k rows (8192 rows), with two rows active at a time, this requires a minimum of 64 ms test time. This time, however, is typically greater than 64 ms because the self-refresh operation is optimized to reduce current consumption and this is usually accomplished through lower self-refresh oscillator frequencies and, thus, a longer self-refresh period. This extra time is not insignificant, because of the large number of DRAMs that are tested routinely.
U.S. Patents pertinent to testing of the self-refresh operation are:
U.S. Pat. No. 5,450,364 (Stephens Jr. et al.) describes a method and apparatus for testing the self-refresh operation of a dynamic memory part. The apparatus provides an oscillator, coupled to a self-refresh counter. The self-refresh counter causes a refresh row address counter to generate row addresses for self-refresh cycles. The refresh row address counter is coupled to a self-refresh control circuit. The self-refresh control circuit is operable to generate a signal indicating completion of a self-refresh cycle. The refresh row address counter is also coupled to a multiplexer. The multiplexer outputs row addresses from either the refresh row address counter or those supplied externally for rows to be refreshed.
U.S. Pat. No. 5,321,661 (Iwakiri et al.) teaches a self-refreshing memory. The self-refreshing memory has a refresh timer that generates refresh requests at a certain rate, and a refresh address counter that generates refresh addresses by counting the refresh requests. A refresh test circuit receives test signals from automatic test equipment that cause it to disable the refresh timer, reset the refresh address counter, then enable the refresh timer for a certain interval. At the end of this interval the refresh test circuit disables the refresh timer again and generates an output signal such as a serial data signal indicating the current refresh address, or a pass-fail signal indicating whether the refresh address is equal to or greater than a preset pass value.
U.S. Pat. No. 5,793,776 (Qureshi et al.) shows a JTAG test logic and a memory controller that places an SDRAM in a self-refresh mode prior to beginning JTAG testing.
U.S. Pat. No. 5,625,597 (Hirose) provides a circuit structure capable of carrying out the function test of the refresh counter and the measurement of the counter cycle at the time of the refresh operation. A test control circuit is provided for carrying out the function test of the refresh counter and the measurement of the counter cycle at the time of the refresh operation, and controls the driving signals so as to set one of the N-channel sense amplifier and the P-channel sense amplifier in a non-active state at the time of a test mode.
It should be noted that none of the above-cited examples of the related art propose to shorten the manufacturing test time in an effort to decrease production costs.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide circuits and a method which allow for a reduction in the manufacturing test time required to verify the self-refresh oscillator frequency of a DRAM.
Another object of the present invention is to be able to signal to the tester when the self-refresh operation has reached a portion of the self-refresh cycle, e.g., when the operation has reached ⅛, ¼, ½, full completion, or any other desired fraction of the self-refresh cycle.
These objects have been achieved when, having invoked the test mode, the DRAM notifies the tester when the self-refresh operation reaches various stages of completion. By signaling the tester after, i.e., ⅛, ¼, ½, etc. of the self-refresh cycle the amount of time needed for verification of the self-refresh oscillator frequency is reduced correspondingly by a factor of 8, 4, or 2. The signaling of a partial test time is achieved by adding self-refresh status logic circuits which decode the high order most significant bits of the refresh address counter and signal the tester that ⅛, ¼, etc. of the cycle have been reached. E.g., the activation of the third most significant bit signals completion of ⅛th of the self-refresh cycle, the activation of the second most significant bit signals completion of ¼th of the self-refresh cycle, the activation of the most significant bit signals completion of ½ of the self-refresh cycle, and deactivation of the most significant bit signals completion of the self-refresh cycle. Any combination of bits may be used to signal a particular partial completion of the self-refresh cycle.
REFERENCES:
patent: 5321661 (1994-06-01), Iwakiri et al.
patent: 5321662 (1994-06-01), Ogawa
patent: 5450364 (1995-09-01), Stephens, Jr. et al.
patent: 5625597 (1997-04-01), Hirose
patent: 5793776 (1998-08-01), Qureshi et al.
patent: 5835401 (1998-11-01), Green et al.
patent: 5995433 (1999-11-01), Liao
patent: 6118710 (2000-09-01), Tsuji
Earl Jeffrey S.
Ematrudo Christopher
Stephens, Jr. Michael C.
Ternullo, Jr. Luigi
Vincent Michael F.
Ackerman Stephen B.
Saile George O.
Tran Andrew Q.
Vanguard International Semiconductor Corp.
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