Self-refresh system for use in a field memory device

Details Self-refresh system for use in a field memory device Self-refresh system for use in a field memory device

1990-11-20

1992-09-08

Gossage, Glenn

Static information storage and retrieval

Read/write circuit

Data refresh

365233, 365236, 36523002, G11C 11406, G11C 11408

Patent

active

051464306

ABSTRACT:
A field memory self-refresh system includes a dynamic random access memory (RAM) having memory cells arranged in a matrix of rows and columns. A row decoder is designated so that the data stored in the memory cells of a row corresponding to the designated row decoder are read out. Subsequently, a row address for refreshing the memory cell array is automatically generated by a refresh address counter which is located in the dynamic RAM, whereby the memory cells on the row of the memory cell array are refreshed without any external refresh control unit. The refresh system includes a refresh RAS signal generating circuit responsive to the output of a column counter. A multiplexer selects the output of a refresh address counter, a plurality of times, between activation of successive rows in response to the refresh RAS signal. Accordingly, it is possible to perform a self-refresh operation in a shortened refresh period.

REFERENCES:
patent: 4677592 (1987-06-01), Sakurai et al.

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